US5398029A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sampling rate converter
Assignee: Seiko NPC Corp
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Filing: 1993-12-21
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Granted: 1995-03-14
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Expires: 2013-12-21
Abstract
Abstract A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.
Inventors
- 👤 Akira Toyama
- 👤 Minoru Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:12
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0621; H03H17/0628; G; G11; G11B; G11B20/00; G11B20/10; G11B20/10527
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
169 words
A sampling rate converter comprising: an arithmetic circuit for performing digital filter processing to convert a first data signal having a first sampling rate into a second data signal having a second sampling rate; a circuit for calculating the sampling rate ratio of said first sampling rate and said second sampling rate; a memory circuit storing a plurality of groups of filter coefficients, for use in digital filter processing performed in said arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges; and a circuit for selecting a filter coefficient group corresponding to said sampling rate ratio, said selecting circuit comprising means whereby, even if a sampling rate ratio calculated by said sampling ratio calculating circuit is outside a sampling rate ratio range corresponding to a filter coefficient group selected thereby at a given time, said selecting circuit continues to select the filter coefficient group selected at said given time as long as said sampling rate ratio is within a predetermined range of said sampling rate ratio range.
Claim 2
Dependent Claim
169 words
A sampling rate converter comprising: an arithmetic circuit for performing digital filter processing to convert a first data signal having a first sampling rate into a second data signal having a second sampling rate; a circuit for calculating the sampling rate ratio of said first sampling rate and said second sampling rate; a memory circuit storing a plurality of groups of filter coefficients, for use in digital filter processing performed in said arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges; and a circuit for selecting a filter coefficient group corresponding to said sampling rate ratio, said selecting circuit comprising means whereby, even if a sampling rate ratio calculated by said sampling ratio calculating circuit is outside a sampling rate ratio range corresponding to a filter coefficient group selected thereby at a given time, said selecting circuit continues to select the filter coefficient group selected at said given time as long as said sampling rate ratio is within a predetermined range of said sampling rate ratio range.
Claim 3
Dependent Claim
119 words
A sampling test converter for converting first digital signals having a first clock rate to second digital signals having a second clock rate, comprising: means for determining the ratio of said first and second clock rates; a memory having stored therein a plurality of groups of digital filter coefficients, each group of which corresponds to a different range of said ratio; and means responsive to said means for determining said ratio for selecting the filter coefficient group corresponding to said ratio at a given time; said responsive means comprising means for continuing to select said selected filter coefficient group as long as said ratio is within a predetermined range of the ratio range of the corresponding filter coefficient group.
Claim 4
Dependent Claim
119 words
A sampling test converter for converting first digital signals having a first clock rate to second digital signals having a second clock rate, comprising: means for determining the ratio of said first and second clock rates; a memory having stored therein a plurality of groups of digital filter coefficients, each group of which corresponds to a different range of said ratio; and means responsive to said means for determining said ratio for selecting the filter coefficient group corresponding to said ratio at a given time; said responsive means comprising means for continuing to select said selected filter coefficient group as long as said ratio is within a predetermined range of the ratio range of the corresponding filter coefficient group.
Claim 5
Dependent Claim
41 words
The sampling rate converter of claim 2 further comprising an arithmetic circuit, means applying said first data signal and signals corresponding to said selected filter coefficient group to said arithmetic circuit, whereby said arithmetic circuit digitally filters said first data signal.
Claim 6
Dependent Claim
33 words
The sampling rate converter of claim 3 further comprising a FIFO coupled to receive the digitally filtered output of said first data signals from said arithmetic circuit for outputting said second digital signals.
Claim 7
Dependent Claim
14 words
The sampling rate converter of claim 2 wherein said ratio ranges overlap one another.
Claim 8
Independent Claim
132 words
A method for converting first digital signals having a first clock rate to second digital signals having a second clock rate, comprising: determining the ratio of said first and second clock rates; storing, in a memory, a plurality of groups of digital filter coefficients, each group of which corresponds to a different range of said ratio; selecting the filter coefficient group corresponding to said ratio at a given time in response to said step of determining said ratio; continuing said selection of said selected filter coefficient group as long as said ratio is within a predetermined range of the ratio range of the corresponding filter coefficient group; and digitally filtering said first data signal in an arithmetic circuit, using said coefficients of selected filter coefficient group, to produce said second digital signals.
Claim 9
Independent Claim
132 words
A method for converting first digital signals having a first clock rate to second digital signals having a second clock rate, comprising: determining the ratio of said first and second clock rates; storing, in a memory, a plurality of groups of digital filter coefficients, each group of which corresponds to a different range of said ratio; selecting the filter coefficient group corresponding to said ratio at a given time in response to said step of determining said ratio; continuing said selection of said selected filter coefficient group as long as said ratio is within a predetermined range of the ratio range of the corresponding filter coefficient group; and digitally filtering said first data signal in an arithmetic circuit, using said coefficients of selected filter coefficient group, to produce said second digital signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |