Patent JPS5650844A successfully refreshed from Google Patents.
US5397906A
Expired / Lapsed
US
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Gate array integrated semiconductor device having stabilized power supply potentials
Assignee: Renesas Electronics Corp
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Filing: 1993-03-30
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Granted: 1995-03-14
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Expires: 2013-03-30
Abstract
Abstract In an unused unit cell of a gate array integrated semiconductor device, a P-type semiconductor region is connected to a ground potential connection and an N-type semiconductor region is connected to a positive power supply connection, thereby reversely-biasing the P-type and N-type semiconductor regions.
Inventors
- 👤 Kouichi Kumagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:40
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/996
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
92 words
A gate array integrated semiconductor device comprising: a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell, whose transistors are never operated, each unused unit cell including a P-type region connected to said first power supply connection and an N-type region connected to said second power supply connection, one of said P-type region and N-type region being formed within the other, thereby reversely-biasing said P-type and N-type regions.
Claim 2
Dependent Claim
92 words
A gate array integrated semiconductor device comprising: a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell, whose transistors are never operated, each unused unit cell including a P-type region connected to said first power supply connection and an N-type region connected to said second power supply connection, one of said P-type region and N-type region being formed within the other, thereby reversely-biasing said P-type and N-type regions.
Claim 3
Dependent Claim
13 words
A device as set forth in claim 1, being of an SOI configuration.
Claim 4
Dependent Claim
13 words
A device as set forth in claim 1, being of an SIMOX configuration.
Claim 5
Dependent Claim
98 words
A gate array integrated semiconductor device comprising; a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell of a P-channel MOS transistor type, whose transistors are never operated, each unused unit cell including an N-type semiconductor region connected to said second power supply connection and P-type semiconductor regions connected to said first power supply connection, said P-type semiconductor regions being formed within said N-type semiconductor region, thereby reversely-biasing said N-type and P-type semiconductor regions.
Claim 6
Dependent Claim
98 words
A gate array integrated semiconductor device comprising; a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell of a P-channel MOS transistor type, whose transistors are never operated, each unused unit cell including an N-type semiconductor region connected to said second power supply connection and P-type semiconductor regions connected to said first power supply connection, said P-type semiconductor regions being formed within said N-type semiconductor region, thereby reversely-biasing said N-type and P-type semiconductor regions.
Claim 7
Dependent Claim
13 words
A device as set forth in claim 4, being of an SOI configuration.
Claim 8
Dependent Claim
13 words
A device as set forth in claim 4, being of an SIMOX configuration.
Claim 9
Dependent Claim
98 words
A gate array integrated semiconductor device comprising; a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher that the first potential; and at least one unused unit cell of a N-channel MOS transistor type, whose transistors are never operated, each unused unit cell including a P-type semiconductor region connected to said first power supply connection and N-type semiconductor regions connected to said second power supply connection, said N-type semiconductor regions being formed within said P-type semiconductor regions, thereby reversely-biasing said P-type and N-type semiconductor regions.
Claim 10
Dependent Claim
98 words
A gate array integrated semiconductor device comprising; a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher that the first potential; and at least one unused unit cell of a N-channel MOS transistor type, whose transistors are never operated, each unused unit cell including a P-type semiconductor region connected to said first power supply connection and N-type semiconductor regions connected to said second power supply connection, said N-type semiconductor regions being formed within said P-type semiconductor regions, thereby reversely-biasing said P-type and N-type semiconductor regions.
Claim 11
Dependent Claim
13 words
A device as set forth in claim 7, being of an SOI configuration.
Claim 12
Dependent Claim
13 words
A device as set forth in claim 7, being of an SIMOX configuration.
Claim 13
Dependent Claim
103 words
A gate array integrated semiconductor device comprising: a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell of an NPN bipolar transistor type, whose transistors are never operated, each unused unit cell including a P-type semiconductor region connected to said first power supply connection and two N-type semiconductor regions sandwiching said P-type semiconductor region, one of said N-type semiconductor regions being connected to said second power supply connection, thereby reversely-biasing said N-type semiconductor region and said P-type semiconductor region.
Claim 14
Dependent Claim
103 words
A gate array integrated semiconductor device comprising: a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell of an NPN bipolar transistor type, whose transistors are never operated, each unused unit cell including a P-type semiconductor region connected to said first power supply connection and two N-type semiconductor regions sandwiching said P-type semiconductor region, one of said N-type semiconductor regions being connected to said second power supply connection, thereby reversely-biasing said N-type semiconductor region and said P-type semiconductor region.
Claim 15
Dependent Claim
13 words
A device as set forth in claim 10, being of an SOI configuration.
Claim 16
Dependent Claim
13 words
A device as set forth in claim 10, being of an SIMOX configuration.
Claim 17
Dependent Claim
103 words
A gate array integrated semiconductor device comprising; a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell of a PNP bipolar transistor type, whose transistors are never operated, each unused unit cell including a N-type semiconductor region connected to said second power supply connection and two P-type semiconductor regions sandwiching said N-type semiconductor region, one of said P-type semiconductor regions being connected to said first power supply connection, thereby reversely-biasing said P-type semiconductor region and said N-type semiconductor region.
Claim 18
Dependent Claim
103 words
A gate array integrated semiconductor device comprising; a first power supply connection for receiving a first potential; a second power supply connection for receiving a second potential which is higher than the first potential; and at least one unused unit cell of a PNP bipolar transistor type, whose transistors are never operated, each unused unit cell including a N-type semiconductor region connected to said second power supply connection and two P-type semiconductor regions sandwiching said N-type semiconductor region, one of said P-type semiconductor regions being connected to said first power supply connection, thereby reversely-biasing said P-type semiconductor region and said N-type semiconductor region.
Claim 19
Dependent Claim
13 words
A device as set forth in claim 13, being of an SOI configuration.
Claim 20
Dependent Claim
13 words
A device as set forth in claim 13, being of an SIMOX configuration.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |