Picture signal processing system having improved quantizer

Claim 2

A picture signal processing system comprising: an orthogonal transformer for performing an orthogonal transformation upon a group of picture signals to generate transformed coefficients G; a quantizer, connected to said orthogonal transformer, for dividing each of the transformed coefficients G by a quantization factor C determined by ##EQU6## where A and B are integers, and S is a sign, said quantizer generating a quantization coefficient G/C for each of the transformed coefficients G; an encoder connected to said quantizer, for encoding each of the quantization coefficients G/C to generate compressed signals of the picture signals.

Claim 3

A system as set forth in claim 1, wherein said quantizer comprises: a first memory means for storing the integers A in accordance with frequency components of the transformed coefficients G; a second memory means for storing the integers B in accordance with the frequency components of the transformed coefficients G; a third memory means for storing the signs S in accordance with the frequency components of the transformed coefficients G; a reading means, connected to said orthogonal transformer, and to said first, second and third memory means, for generating an address signal by counting the transformed coefficients G and reading said first and second memory means by the address signal; a first shifter, connected to said orthogonal transformer and to said first memory means, for shifting each of the transformed coefficients G by a number of bits corresponding to the integer A read from said first memory means; a calculating means, connected to said orthogonal transformer, to said first shifter, and to said third memory means, for performing a calculating between each of the transformed coefficients G and the output of said first shifter in accordance with the sign S read from said third memory means; and a second shifter, connected to said calculating means, for shifting the output of said calculating means by a number of bits corresponding to the integer B read from said second memory means.

Claim 4

A system as set forth in claim 2, wherein said calculating means comprises: an adder, connected to said orthogonal transformer and to said first shifter, for adding the output of said first shifter to each of the transformed coefficients G; a subtractor, connected to said orthogonal transformer and to said first shifter, for subtracting the output of said first shifter from each of the transformed coefficients G; and a selector, connected to said adder, to said subtractor, and to said third memory means, for selecting one of the outputs of said adder and said subtractor in accordance with the sign S read from said third memory means.

Claim 5

A system as set forth in claim 1, wherein said orthogonal transformer comprises a discrete cosine transformer (DCT).

Claim 6

A system as set forth in claim 2, wherein the group of picture signals include N×N, wherein N is an integer (N=2, 3, . . . ) picture signals, said reading means comprising an N×N-ary counter.

Claim 7

A picture signal processing system comprising: an orthogonal transformer for performing an orthogonal transformation upon a group of picture signals to generate transformed coefficients G; a first memory means for storing non-negative integers A' in accordance with frequency components of the transformed coefficients G; a second memory means for storing non-negative integers B' in accordance with the frequency components of the transformed coefficients G; a third memory means for storing signs S in accordance with the frequency components of the transformed coefficients G; a counter, connected to said orthogonal transformer, and to said first, second and third memory means for generating an address signal by counting the transformed coefficients G and reading said first and second memory means by the address signal, said counter being reset by every group of the transformed coefficients; a first right shifter, connected to said orthogonal transformer and to said first memory means, for shifting each of the transformed coefficients G in the right direction by a number of bits corresponding to the integer A' read from said first memory means; an adder, connected to said orthogonal transformer and to said first shifter, for adding the output of said first shifter to each of the transformed coefficients G; a subtractor, connected to said orthogonal transformer and to said first shifter, for subtracting the output of said first shifter from each of the transformed coefficients G; a selector, connected to said adder, to said subtractor, and to said third memory means, for selecting one of the outputs of said adder and said subtractor in accordance with the sign S read from said third memory means; and a second right shifter, connected to said selector, for shifting the output of said selector on the right direction by a number of bits corresponding to the integer B' read from said second memory means.

Claim 8

A picture signal processing system comprising: an orthogonal transformer for performing an orthogonal transformation upon a group of picture signals to generate transformed coefficients G; a first memory means for storing non-negative integers A' in accordance with frequency components of the transformed coefficients G; a second memory means for storing non-negative integers B' in accordance with the frequency components of the transformed coefficients G; a third memory means for storing signs S in accordance with the frequency components of the transformed coefficients G; a counter, connected to said orthogonal transformer, and to said first, second and third memory means for generating an address signal by counting the transformed coefficients G and reading said first and second memory means by the address signal, said counter being reset by every group of the transformed coefficients; a first right shifter, connected to said orthogonal transformer and to said first memory means, for shifting each of the transformed coefficients G in the right direction by a number of bits corresponding to the integer A' read from said first memory means; an adder, connected to said orthogonal transformer and to said first shifter, for adding the output of said first shifter to each of the transformed coefficients G; a subtractor, connected to said orthogonal transformer and to said first shifter, for subtracting the output of said first shifter from each of the transformed coefficients G; a selector, connected to said adder, to said subtractor, and to said third memory means, for selecting one of the outputs of said adder and said subtractor in accordance with the sign S read from said third memory means; and a second right shifter, connected to said selector, for shifting the output of said selector on the right direction by a number of bits corresponding to the integer B' read from said second memory means.

Claim 9

A system as set forth in claim 6, wherein said orthogonal transformer comprises a discrete cosine transformer (DCT).

Claim 10

A system as set forth in claim 6, where the group of picture signals include N×N, wherein N is an integer (N=2, 3, . . . ) picture signals, said counter comprising an N×N-ary counter.