Erasable and programmable seven segment display driver

Claim 1

An erasable and programmable seven segment display driver, comprising: an oscillator for providing oscillating signal; a signal source selector for providing a signal source, which comprises a frequency divider and a multiplexer, the frequency divider receiving and dividing the oscillating signal sent from the oscillator into a lower frequency signal, the multiplexer providing a path for outputting the signal source sent from the frequency divider or an external clock signal; during programming, the external clock signal is supplied to the multiplexer, while during data reading, the oscillating signal is divided by the frequency divider and passes through the multiplexer; a column address generator comprising a column address counter and a common signal generator, the column address counter receiving the signal source sent from the signal source selector and generating a column address signal, the common signal generator being used to generate a common signal; a row address generator comprising a row address counter and a data latch signal generator, the row address counter receiving the signal source sent from the signal source selector and generating a row address signal to an erasable and programmable read-only memory array, the data latch signal generator receiving the row address signal sent from the row address counter and the signal source of the signal source selector to generate a segment signal; a seven segment display for displaying numerical display data; said erasable and programmable read-only memory array being provided for storing a set of display data and the data being sent to the seven segment display in accordance with the column address signal of the column address generator and the row address signal of the row address generator; a common signal driver which serves as an amplifier circuit capable of amplifying the common signal sent from the column address generator; and a segment signal driver for receiving the segment signal of the row address generator, comprising a data register and a current amplifier.