Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a main select line group having first and second select lines; a redundancy select line group having third and fourth select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to first and second control signals, the first select line activation circuit activating the first select line when the first control signal is at a first potential level and activating the second select line when the first control signal is at a second potential level; a second select line activation circuit for activating one of the select lines of the redundancy select line group in response to the first and second control signals, the second select line activation circuit activating the third select line when the first control signal is at the first potential level and activating the fourth select line when the first control signal is at the second potential level; a first conductive. line having a first terminal to receive one of the first control signal and a supply signal having substantially the same potential level as the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially the same potential level as that of one of the first and second potential levels when the first conductive portion is blown; a second conductive line having a second terminal to receive a third control signal, complementary to the first control signal, a second node coupled to the second terminal and a second conductive portion connected between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially the same potential level as that of one of the first and second potential levels when the second conductive portion is blown; and a control signal generating circuit for outputting the second control signal to the second select line activation circuit when the potential level at the first node and the potential level at the second node have a given relation with respect to each other, and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 3

A semiconductor memory device according to claim 1, wherein the first potential supply circuit has a first potential holding circuit for causing the first node to be substantially at one of the first and second potential levels when the first conductive portion is blown; and wherein the second potential supply circuit has a second potential holding circuit for causing the second node to be substantially at one of the first and second potential levels when the second conductive portion is blown.

Claim 4

A semiconductor memory device according to claim 2, wherein the given relation is that both the first and second nodes are at one of the first and second potential levels.

Claim 5

A semiconductor memory device according to claim 2, wherein the first select line activation circuit is responsive to a third control signal; wherein the first select line is coupled to the first control signal and the second select line is coupled to the third control signal; wherein the second select line activation circuit is responsive to the third control signal; wherein the third select line is coupled to the first control signal and the fourth select line is coupled to the third control signal; and wherein the second and fourth select lines are activated when the third control signal is substantially at the first potential level.

Claim 6

A semiconductor memory device according to claim 4, wherein the given relation is that both the first and second nodes are at the first potential level.

Claim 7

A semiconductor memory device according to claim 4, wherein each of the first to fourth select lines includes a plurality of word lines; wherein the first select line activation circuit is responsive to fourth control signal to thereby cause one word line among the first and second select lines to be active; and wherein the second select line activation circuit is responsive to the fourth control signal to thereby cause one word line among the third and fourth select lines to be active.

Claim 8

A semiconductor memory device according to claim 6, wherein each of the first to fourth select lines is activated when one of the word lines belonging to each of the first to fourth select lines is active.

Claim 9

A semiconductor memory device according to claim 1, wherein each of the first to fourth select lines has a plurality of word lines; wherein the first select line activation circuit is responsive to fourth control signal to thereby cause one word line among the first and second select lines to be active; and wherein the second select line activation circuit is responsive to a fourth control signal to thereby cause one word line among the third and fourth select lines to be active.

Claim 10

A semiconductor memory device according to claim 8, wherein each of the first to fourth select lines is activated when one of the word lines belonging to each of the first to fourth select lines is active.

Claim 11

A semiconductor memory device according to claim 1, wherein the given relation is that the first node is at the first potential level and the second node is at the second potential level.

Claim 12

A semiconductor memory device comprising: a main select line group having first and second select lines; a redundancy select line group having third and fourth select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to first and second control signals, the first select line activation circuit activating the first select line when the first control signal is at a first potential level and activating the second select line when the first control signal is at a second potential level; a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the first and second control signals, the second select line activation circuit activating the third select line when the first control signal is at the first potential level and activating the fourth select line when the first control signal is at the second potential level; a first conductive line having a first terminal to receive the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially the same potential level as that of one of the first and second potential levels when the first conductive portion is blown; a second conductive line having a second terminal to receive one of the first control signal and a supply control signal which is substantially equivalent to the first control signal, a second node coupled to the second terminal and a second conductive portion connected between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially the same potential level as one of the first and second potential levels when the second conductive portion is blown; and a control signal generating circuit for outputting the second control signal to the second select line activation circuit when the first node and the second node have a given relation with respect to each other and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 13

A semiconductor memory device comprising: a main select line group having first and second select lines; a redundancy select line group having third and fourth select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to first and second control signals, the first select line activation circuit activating the first select line when the first control signal is at a first potential level and activating the second select line when the first control signal is at a second potential level; a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the first and second control signals, the second select line activation circuit activating the third select line when the first control signal is at the first potential level and activating the fourth select line when the first control signal is at the second potential level; a first conductive line having a first terminal to receive the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially the same potential level as that of one of the first and second potential levels when the first conductive portion is blown; a second conductive line having a second terminal to receive one of the first control signal and a supply control signal which is substantially equivalent to the first control signal, a second node coupled to the second terminal and a second conductive portion connected between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially the same potential level as one of the first and second potential levels when the second conductive portion is blown; and a control signal generating circuit for outputting the second control signal to the second select line activation circuit when the first node and the second node have a given relation with respect to each other and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 14

A semiconductor memory device according to claim 11, wherein the first potential supply circuit has a first potential holding circuit for causing the first node to be substantially at one of the first and second potential levels when the first conductive portion is blown; and wherein the second potential supply circuit has a second potential holding circuit for causing the second node to be substantially at the other one of the first and second potential levels when the second conductive portion is blown.

Claim 15

A semiconductor memory device according to claim 12, wherein the first select line activation circuit is further responsive to a third control signal; wherein the first select line is coupled to the first control signal and the second select line is coupled to the third control signal; wherein the second select line activation circuit is further responsive to the third control signal; wherein the third select line is coupled to the first control signal and the fourth select line is coupled to the third control signal; and wherein the second and fourth select lines are active when the third control signal is substantially at the first potential level.

Claim 16

A semiconductor memory device according to claim 13, wherein the given relation is that the first node is at the first potential level and the second node is at the second potential level.

Claim 17

A semiconductor memory device according to claim 13, wherein each of the first to fourth select lines includes a plurality of word lines; wherein the first select line activation circuit is responsive to a fourth control signal to thereby cause one word line among the first and second select lines to be active; and wherein the second select line activation circuit is responsive to the fourth control signal to thereby cause one word line among the third and fourth select lines to be active.

Claim 18

A semiconductor memory device according to claim 15, wherein each of the first to fourth select lines is activated when one of the word lines belonging to each of the first to fourth select lines is active.

Claim 19

A semiconductor memory device according to claim 11, wherein each of the first to fourth select lines has a plurality of word lines; wherein the first select line activation circuit is responsive to a fourth control signal to thereby cause one word line among the first and second select lines to be active; and wherein the second select line activation circuit is responsive to the fourth control signal to thereby cause one word line among the third and fourth select lines to be active.

Claim 20

A semiconductor memory device according to claim 17, wherein each of the first to fourth select lines is activated when one of the word lines belonging to each of the first to fourth select lines is active.

Claim 21

A semiconductor memory device comprising: a main select line group and a redundancy select line group, each having a plurality of select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to a plurality of address control signals including a second control signal; a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the address control signals including the second control signal; a first conductive line having a first terminal to receive one of a first control signal included in the address control signals and a supply signal substantially equivalent to the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially one of first and second potential levels when the first conductive portion is blown; a second conductive line having a second terminal to receive a third control signal complementary to the first control signal, a second node coupled to the second terminal and a second conductive portion connected between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially one of the first and second potential levels when the second conductive portion is blown; and a control circuit for outputting the second control signal to the second select line activation circuit when the potential level at the first node and the potential level at the second node have a given relation with respect to each other, and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 22

A semiconductor memory device comprising: a main select line group and a redundancy select line group, each having a plurality of select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to a plurality of address control signals including a second control signal; a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the address control signals including the second control signal; a first conductive line having a first terminal to receive one of a first control signal included in the address control signals and a supply signal substantially equivalent to the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially one of first and second potential levels when the first conductive portion is blown; a second conductive line having a second terminal to receive a third control signal complementary to the first control signal, a second node coupled to the second terminal and a second conductive portion connected between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially one of the first and second potential levels when the second conductive portion is blown; and a control circuit for outputting the second control signal to the second select line activation circuit when the potential level at the first node and the potential level at the second node have a given relation with respect to each other, and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 23

A semiconductor memory device according to claim 19, wherein the first potential supply circuit has a first potential holding circuit for causing the first node to be substantially at one of the first and second potential levels when the first conductive portion is blown, and wherein the second potential supply circuit has a second potential holding circuit for causing the second node to be substantially at one of the first and second potential levels when the second conductive portion is blown.

Claim 24

A semiconductor memory device according to claim 20, wherein the given relation is that both the first and the second nodes are at one of the first and the second potential levels.

Claim 25

A semiconductor memory device according to claim 19, wherein the first and second conductive portions are fuse elements.

Claim 26

A semiconductor memory device according to claim 22, wherein the first potential supply circuit has a first potential holding circuit for causing the first node to be substantially at one of the first and second potential levels when the first conductive portion is blown, and wherein the second potential supply circuit has a second potential holding circuit for causing the second node to be substantially at one of the first and second potential levels when the second conductive portion is blown.

Claim 27

A semiconductor memory device according to claim 23, wherein the given relation is that both the first and second nodes are at one of the first and the second potential levels.

Claim 28

A semiconductor memory device according to claim 19, wherein the plurality of address control signals each are substantially at one of the first potential level and the second potential level.

Claim 29

A semiconductor memory device comprising: a main select line group and a redundancy select line group, each having a plurality of select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to a plurality of address control signals including a second control signal; a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the address control signals including the second control signal; a first conductive line having a first terminal to receive one of a first control signal included in the address control signals and a reference signal substantially equivalent to the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially one of first and second potential level when the first conductive portion is blown; a second conductive line having a second terminal to receive one of said first control signals and a supply signal substantially equivalent to the first control signal, a second node coupled to the second terminal and a second conductive portion connecting between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially one of the first and second potential levels when the second conductive portion is blown; and a control circuit for outputting the second control signal to the second select line activation circuit when the potential level at the first node and the potential level at the second node have a given relation to each other, and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 30

A semiconductor memory device comprising: a main select line group and a redundancy select line group, each having a plurality of select lines; a first select line activation circuit for activating one of the select lines in the main select line group in response to a plurality of address control signals including a second control signal; a second select line activation circuit for activating one of the select lines in the redundancy select line group in response to the address control signals including the second control signal; a first conductive line having a first terminal to receive one of a first control signal included in the address control signals and a reference signal substantially equivalent to the first control signal, a first node coupled to the first terminal and a first conductive portion connected between the first terminal and the first node; a first potential supply circuit for causing the first node to be at substantially one of first and second potential level when the first conductive portion is blown; a second conductive line having a second terminal to receive one of said first control signals and a supply signal substantially equivalent to the first control signal, a second node coupled to the second terminal and a second conductive portion connecting between the second terminal and the second node; a second potential supply circuit for causing the second node to be at substantially one of the first and second potential levels when the second conductive portion is blown; and a control circuit for outputting the second control signal to the second select line activation circuit when the potential level at the first node and the potential level at the second node have a given relation to each other, and outputting the second control signal to the first select line activation circuit when said given relation does not exist.

Claim 31

A semiconductor memory device according to claim 26, wherein the first potential supply circuit has a first potential holding circuit for causing the first node to be substantially at one of the first and second potential levels when the first conductive portion is blown, and wherein the second potential supply circuit has a second potential holding circuit for causing the second node to be substantially at the other one of the first and second potential levels when the second conductive portion is blown.

Claim 32

A semiconductor memory device according to claim 27, wherein the given relation is that the first node is at one of the potential levels and the second node is at the other potential level.

Claim 33

A semiconductor memory device according to claim 26, wherein the first and second conductive portions are fuse elements.

Claim 34

A semiconductor memory device according to claim 26, wherein the plurality of address control signals each are substantially at one of the first and second potential levels.

Claim 35

A semiconductor memory device comprising: a first conductive line having a first terminal, a first node and a first conductive portion connecting between the first terminal and the first node; a first potential supply circuit for causing the first node to be at a first potential level when the first conductive portion is blown; a second conductive line having a second terminal, a second node and a second conductive portion connecting between the second terminal and the second node; a second potential supply circuit for causing the second node to be at a further potential level having a first given potential relation to the first potential level when the second conductive portion is blown; a drive circuit for driving the first and second terminals at potential levels having a second given potential relation; and a detecting circuit for detecting whether a given potential relation between the first and second nodes is either the first given potential relation or the second given potential relation.

Claim 36

A semiconductor memory device comprising: a first conductive line having a first terminal, a first node and a first conductive portion connecting between the first terminal and the first node; a first potential supply circuit for causing the first node to be at a first potential level when the first conductive portion is blown; a second conductive line having a second terminal, a second node and a second conductive portion connecting between the second terminal and the second node; a second potential supply circuit for causing the second node to be at a further potential level having a first given potential relation to the first potential level when the second conductive portion is blown; a drive circuit for driving the first and second terminals at potential levels having a second given potential relation; and a detecting circuit for detecting whether a given potential relation between the first and second nodes is either the first given potential relation or the second given potential relation.

Claim 37

A semiconductor memory device according to claim 31, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level, and the second given potential relation is that the second terminal is substantially at a second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 38

A semiconductor memory device according to claim 31, wherein the first given potential relation is that the second node is substantially at a second potential level when the first node is substantially at the first potential level, and wherein the second given potential relation is that both the first and second terminals are substantially at the same potential level.

Claim 39

A semiconductor memory device according to claim 31, further comprising a main memory cell group having a plurality of memory cells and a redundancy memory cell group having a plurality of memory cells, wherein the redundancy memory cell group is accessible when the detecting circuit detects the first given potential relation and the main memory cell group is accessible when the detecting circuit detects the second given potential relation.

Claim 40

A semiconductor memory device according to claim 34, wherein the main memory cell group has a first main memory cell group having a plurality of memory cells and a second main memory cell group having a plurality of memory cells; wherein the second given potential relation has first and second states; wherein the first main memory cell group is accessible when the detecting circuit detects the second given potential relation at the first state; and wherein the second main memory cell group is accessible when the detecting circuit detects the second given potential relation at the second state.

Claim 41

A semiconductor memory device according to claim 35, wherein the redundancy memory cell group comprises a first redundancy memory cell group having a plurality of memory cells and a second redundancy memory cell group having a plurality of memory cells; wherein the first redundancy memory cell group is accessible when the detecting circuit detects the first given potential relation if the second given potential relation is at the first state; and wherein the second redundancy memory cell group is accessible when the detecting circuit detects the first given potential relation if the second given potential relation is at the second state.

Claim 42

A semiconductor memory device according to claim 36, wherein the first main memory cell group is coupled to a first select line, wherein the second main memory cell group is coupled to a second select line; wherein the first redundancy memory cell group is coupled to a third select line; wherein the second redundancy memory cell group is coupled to a fourth select line; wherein the first select line and the second select line are coupled to a first select line activation circuit; wherein the third select line and the fourth select line are coupled to a second select line activation circuit ; wherein the first select line activation circuit is responsive to a first control signal for thereby activating the first select line when the first control signal is at the first potential level and activating the second select line when the first control signal is at a second potential level; wherein the second select line activation circuit is responsive to the first control signal for thereby activating the third select line when the first control signal is at the first potential level and activating the fourth select line when the first control signal is at the second potential level; wherein the drive circuit outputs the first control signal; and wherein the first terminal receives either the first control signal or a signal representing a potential level substantially the same as that of the first control signal from the drive circuit.

Claim 43

A semiconductor memory device according to claim 37, wherein the first select line activation circuit is responsive to a second control signal and the first control signal to thereby activate one of the first and second select lines; wherein the second select line activation circuit is responsive to the second control signal and the first control signal to thereby activate one of the third and fourth select lines; wherein the detecting circuit applies the second control signal to the second select line activation circuit when the detecting circuit detects the first given potential relation; and wherein the detecting circuit applies the second control signal to the first select line activation circuit when the detecting circuit detects the second given potential relation.

Claim 44

A semiconductor memory device according to claim 38, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level, and the second given potential relation is that the second terminal is substantially at the second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level when the second terminal is substantially at the first potential level.

Claim 45

A semiconductor memory device according to claim 38, wherein the first given potential relation is that the second node is substantially at the first potential level when the first node is substantially at the first potential level; and wherein the second given potential relation is that both the first and second terminals are at substantially the same potential level.

Claim 46

A semiconductor memory device according to claim 38, wherein the first and second conductive portions are fuse elements.

Claim 47

A semiconductor memory device according to claim 38, wherein the first and second control signals are address signals.

Claim 48

A semiconductor memory device according to claim 38, wherein each of the first to fourth select lines includes a plurality of word lines; wherein the first select line activation circuit is responsive to the third control signal to thereby activate one word line among the first and second select lines; and wherein the second select line activation circuit is responsive to the third control signal to thereby activate one word line among the third and fourth select lines.

Claim 49

A semiconductor memory device according to claim 43, wherein each of the first to fourth select lines is activated when one of the word lines among the first to fourth select lines belonging thereto is active.

Claim 50

A semiconductor memory device according to claim 36, wherein a plurality of memory cells belong to a memory cell array having first and second subarrays.

Claim 51

A semiconductor memory device according to claim 45, wherein the first main memory cell group and the first redundancy memory cell group belong to the first subarray; and wherein the second main memory cell group and the second redundancy memory cell group belong to the second subarray.

Claim 52

A semiconductor memory device according to claim 45, wherein the drive circuit is a subarray selecting circuit for outputting first and second control signals.

Claim 53

A semiconductor memory device according to claim 47, wherein the first subarray receives the first control signal and is accessible when the first control signal is substantially at the first potential level and is unaccessible when the first control signal is substantially at a second potential level; wherein the second subarray receives the second control signal and is accessible when the second control signal is substantially at the first potential level and is unaccessible when the second control signal is substantially at the second potential level; and wherein the subarray selecting circuit outputs the second control signal substantially at the second potential level when the first control signal is substantially at the first potential level, and outputs the first control signal substantially at the second potential level when the second control signal is substantially at the first potential level.

Claim 54

A semiconductor memory device according to claim 48, wherein the drive circuit applies the first control signal to the first terminal and applies the second control signal to the second terminal.

Claim 55

A semiconductor memory device according to claim 49, wherein the first given potential relation is that the first and second nodes are substantially at the same potential level, and wherein the second given potential relation is that the second terminal is substantially at the second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 56

A semiconductor memory device according to claim 48, further comprising first and second column lines, both coupled to the first and second subarrays, wherein the first column line is coupled to the first and second main memory cell groups and is active upon reception of a third control signal; and wherein the second column line is coupled to the first and second redundancy memory cell groups and is active upon reception of the third control signal.

Claim 57

A semiconductor memory device according to claim 51, wherein the detecting circuit applies the third control signal to the first column line when the detecting circuit detects the second given potential relation and applies the third control signal to the second column line when the detecting circuit detects the second given potential relation.

Claim 58

A semiconductor memory device according to claim 52, wherein the first state corresponds to a state where the first control signal is at the first potential level and the second state corresponds to a state where the second control signal is at the first potential level.

Claim 59

A semiconductor memory device according to claim 53, wherein the drive circuit applies the first control signal to the first terminal and applies the second control signal to the second terminal.

Claim 60

A semiconductor memory device according to claim 54, wherein the first given potential relation is that the second node is substantially at the same potential level, and wherein the second given potential relation is that the second terminal is substantially at the second potential level when the first terminal is substantially at the first potential level and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 61

A semiconductor memory device comprising: a first conductive line having a first terminal, a first node and a first conductive portion connecting between the first terminal and the first node; a first potential supply circuit for causing the first node to be at a first potential level when the first conductive portion is blown; a second conductive line having a second terminal, a second node and a second conductive portion connecting between the second terminal and the second node; a second potential supply circuit for causing the second node to be at the first potential level and at a further potential level having a first given potential relation to the first potential level when the second conductive portion is blown; a drive circuit for driving the first terminal and the second terminal at potential levels having a second given potential relation and outputting a first control signal; first and second controlled circuits being responsive to a second control signal and the first control signal; and a first detecting circuit for detecting whether a given potential relation between the first and second nodes is the first given potential relation or the second given potential relation, wherein the first detecting circuit applies the second control signal to the second controlled circuit when it detects the first given potential relation, and applies the second control signal to the first controlled circuit when it detects the second given potential relation.

Claim 62

A semiconductor memory device comprising: a first conductive line having a first terminal, a first node and a first conductive portion connecting between the first terminal and the first node; a first potential supply circuit for causing the first node to be at a first potential level when the first conductive portion is blown; a second conductive line having a second terminal, a second node and a second conductive portion connecting between the second terminal and the second node; a second potential supply circuit for causing the second node to be at the first potential level and at a further potential level having a first given potential relation to the first potential level when the second conductive portion is blown; a drive circuit for driving the first terminal and the second terminal at potential levels having a second given potential relation and outputting a first control signal; first and second controlled circuits being responsive to a second control signal and the first control signal; and a first detecting circuit for detecting whether a given potential relation between the first and second nodes is the first given potential relation or the second given potential relation, wherein the first detecting circuit applies the second control signal to the second controlled circuit when it detects the first given potential relation, and applies the second control signal to the first controlled circuit when it detects the second given potential relation.

Claim 63

A semiconductor memory device according to claim 56, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level, and the second given potential relation is that the second terminal is substantially at a second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 64

A semiconductor memory device according to claim 56, wherein the first given potential relation is that the second node is substantially at the second potential level when the first node is substantially at the first potential level; and wherein the second given potential relation is that both the first and second terminals are substantially at the same potential level.

Claim 65

A semiconductor memory device according to claim 56, further comprising a main memory cell group having a plurality of memory cells and a redundancy memory cell group having a plurality of memory cells, wherein the redundancy memory cell group is accessible when the first detecting circuit detects the first given potential relation and the main memory cell group is accessible when the detecting circuit detects the second given potential relation.

Claim 66

A semiconductor memory device according to claim 59, wherein the main memory cell group has a first main memory cell group having a plurality of memory cells and a second main memory cell group having a plurality of memory cells; wherein the second given potential relation has first and second states; wherein the first main memory cell group is accessible when the detecting circuit detects the second given potential relation if the second given potential relation is at the first state; and wherein the second main memory cell group is accessible when the detecting circuit detects the second given potential relation if the second given potential relation is at the second state.

Claim 67

A semiconductor memory device according to claim 60, wherein the redundancy memory cell group has a first redundancy memory cell group having a plurality of memory cells and a second redundancy memory cell group having a plurality of memory cells; wherein the first redundancy memory cell group is accessible when the detecting circuit detects the first given potential relation if the second given potential relation is at the first state; and wherein the second redundancy memory cell group is accessible when the detecting circuit detected the first given potential relation if the second given potential relation is at the second state.

Claim 68

A semiconductor memory device according to claim 61, wherein the first main memory cell group is coupled to a first select line; wherein the second main memory cell group is coupled to a second select line; wherein the first redundancy memory cell group is coupled to a third select line; wherein the second redundancy memory cell group is coupled to a fourth select line; wherein the first select line and the second select line are coupled to the first controlled circuit; wherein the third select line and the fourth select line are coupled to the second controlled circuit; wherein the first controlled circuit is responsive to the first control signal for thereby activating the first select line when the first control signal is at the first potential level and activating the second select line when the first control signal is at a second potential level; wherein the second controlled circuit is responsive to the first control signal for thereby activating the third select line when the first control signal is at the first potential level and activating the fourth select line when the first control signal is at the second potential level; wherein the drive circuit outputs the first control signal; and wherein the first terminal receives the first control signal or a signal representing the potential level substantially the same as that of the first control signal from the drive means.

Claim 69

A semiconductor memory device according to claim 62, wherein the first controlled circuit activates one of the first and second select lines in response to the second control signal and the first control signal; and wherein the second controlled circuit activates one of the third and fourth select lines in response to the second control signal and the first control signal.

Claim 70

A semiconductor memory device according to claim 63, wherein the first controlled circuit corresponds to a first select line activation circuit and the second controlled circuit corresponds to a second select line activation circuit.

Claim 71

A semiconductor memory device according to claim 64, wherein the first given potential relation is that both the first and second nodes are at the first potential level; and wherein the second given potential relation is that the second terminal is substantially at the second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 72

A semiconductor memory device according to claim 64, wherein the first given potential relation is that the second node is substantially at the second potential level when the first node is substantially at the first potential level; and wherein the second given potential relation is that both the first and second terminals are at substantially the same potential level.

Claim 73

A semiconductor memory device according to claim 64, wherein the first and second conductive portions are fuse elements.

Claim 74

A semiconductor memory device according to claim 64, wherein the first and second control signals are address signals.

Claim 75

A semiconductor memory device according to claim 64, wherein each of the first to fourth select lines includes a plurality of word lines; wherein the first select line activation circuit receives the third control signal to thereby cause one word line among the first and second select lines to be active; and wherein the second select line activation circuit receives the third control signal to thereby cause one word line among the third and fourth select lines to be active.

Claim 76

A semiconductor memory device according to claim 69, wherein each of the first to fourth select lines is activated when one of the word lines belonging thereto is active.

Claim 77

A semiconductor memory device according to claim 56, wherein the first terminal receives one of the first control signal and a signal synchronous with the first control signal; wherein the first control signal is changed from the first potential level to a second potential level or is changed from the second potential level to the first potential level; and wherein the second terminal receives a third control signal having the second given potential relation to the first control signal.

Claim 78

A semiconductor memory device according to claim 71, further including a second detecting circuit coupled to the first and second terminals for detecting that one of the first control signal and the signal synchronous with the first control signal have the given potential relation to the third control signal; wherein the second detecting circuit applies a fourth control signal to the first detecting circuit after the lapse of a first given time from a time of detection; and wherein the first detecting circuit applies the second control signal to the second controlled circuit on reception of the fourth control signal.

Claim 79

A semiconductor memory device according to claim 72, wherein the first node receives the first control signal after the lapse of a second given time from a time that the first terminal received the first control signal if the first conductive portion is blown; and wherein the first given time is longer than the second given time.

Claim 80

A semiconductor memory device according to claim 73, wherein the second detecting circuit includes a delay circuit; and wherein the first given time is set by the delay circuit.

Claim 81

A semiconductor memory device according to claim 74, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level, and the second given potential relation is that the second terminal is substantially at the second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 82

A semiconductor memory device according to claim 71, wherein the first terminal receives the first control signal through a first inverter circuit; wherein the second terminal receives the third control signal through a second inverter circuit; and wherein the drive circuit outputs the first and third control signals having the second given potential relation to each other during an operating time and outputs the first and third control signals, both at the second potential level during a non-operating time.

Claim 83

A semiconductor memory device according to claim 76, wherein the first and second potential supply circuit cause the first and second nodes to be at the first potential level during the non-operating time.

Claim 84

A semiconductor memory device according to claim 77, further including a second detecting circuit coupled to the first and second terminals for detecting that one of the first control signal and the signal synchronous with the first control signal, and the third control signal have the second given potential relation; wherein the second detecting circuit applies a fourth control signal to the first detecting circuit after the lapse of a first given time from a time of detection; and wherein the first detecting circuit applies the second control signal to the second controlled circuit after receiving the fourth control signal.

Claim 85

A semiconductor memory device according to claim 78, wherein the first node receives the first control signal at the lapse of a second given time from a time that the first terminal received the first control signal if the first conductive portion is blown; and wherein the first given time is longer than the second given time.

Claim 86

A semiconductor memory device according to claim 79, wherein the second detecting circuit includes a delay circuit; and wherein the first given time is set by the delay circuit.

Claim 87

A semiconductor memory device according to claim 80, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level, and the second given potential relation is that the second terminal is substantially at the second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 88

A semiconductor memory device comprising; a first conductive line having a first terminal, first and third nodes, a first conductive portion connecting between the first terminal and the first node and a third conductive portion connecting between the first and the third nodes; a first potential supply circuit for causing the first and third nodes to be at a first potential level when the first conductive portion is blown and causing the third node to be at the first potential level when the third conductive portion is blown; a second conductive line having a second terminal and second and fourth nodes, a second conductive portion connecting between the second terminal and the second node and a fourth conductive portion connecting between the second and the fourth nodes; a second potential supply circuit for causing the second and fourth nodes to be at the first potential level and at a further potential level having a first given potential relation to the first potential level when the second conductive portion is blown, and causing the fourth node to be at the first potential level and at the further potential level having the first given potential relation to the first potential level when the fourth conductive portion is blown; a drive circuit for driving the first terminal and the second terminal at potential levels having a second given potential relation and for outputting a first control signal; first, second and third controlled circuits being responsive to a second control signal and the first control signal; a first detecting circuit for detecting whether a given potential relation between the first and second nodes is the first given potential relation or the second given potential relation, wherein the first detecting circuit applies the second control signal to the second controlled circuit when the first detecting circuit detects the first given potential relation and applies the second control signal to the first controlled circuit when the first detecting circuit detects the second given potential relation; and a third detecting circuit for detecting whether a further given potential relation between the third and forth nodes is the first given potential relation or the second given potential relation, wherein the third detecting circuit applies the second control signal to the third controlled circuit when the third detecting circuit detects the first given potential relation and applies the second control signal to the second controlled circuit when the third detecting circuit detects the second given potential relation.

Claim 89

A semiconductor memory device comprising; a first conductive line having a first terminal, first and third nodes, a first conductive portion connecting between the first terminal and the first node and a third conductive portion connecting between the first and the third nodes; a first potential supply circuit for causing the first and third nodes to be at a first potential level when the first conductive portion is blown and causing the third node to be at the first potential level when the third conductive portion is blown; a second conductive line having a second terminal and second and fourth nodes, a second conductive portion connecting between the second terminal and the second node and a fourth conductive portion connecting between the second and the fourth nodes; a second potential supply circuit for causing the second and fourth nodes to be at the first potential level and at a further potential level having a first given potential relation to the first potential level when the second conductive portion is blown, and causing the fourth node to be at the first potential level and at the further potential level having the first given potential relation to the first potential level when the fourth conductive portion is blown; a drive circuit for driving the first terminal and the second terminal at potential levels having a second given potential relation and for outputting a first control signal; first, second and third controlled circuits being responsive to a second control signal and the first control signal; a first detecting circuit for detecting whether a given potential relation between the first and second nodes is the first given potential relation or the second given potential relation, wherein the first detecting circuit applies the second control signal to the second controlled circuit when the first detecting circuit detects the first given potential relation and applies the second control signal to the first controlled circuit when the first detecting circuit detects the second given potential relation; and a third detecting circuit for detecting whether a further given potential relation between the third and forth nodes is the first given potential relation or the second given potential relation, wherein the third detecting circuit applies the second control signal to the third controlled circuit when the third detecting circuit detects the first given potential relation and applies the second control signal to the second controlled circuit when the third detecting circuit detects the second given potential relation.

Claim 90

A semiconductor memory device according to claim 82, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level; and wherein the second given potential relation is that the second terminal is substantially at a second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 91

A semiconductor memory device according to claim 82, wherein the first given potential relation is that when one of the first and second nodes is substantially at the first potential level, one of the third and fourth nodes is substantially at the second potential level, respectively; and wherein the second given potential relation is that both the first and second terminals are substantially at the same potential level.

Claim 92

A semiconductor memory device according to claim 82, further comprising first and second main memory cell groups, both having a plurality of memory cells, and a redundancy memory cell group having a plurality of memory cells; wherein the second main memory cell group is accessible when the first detecting circuit detects the first given potential relation and the first main memory cell group is accessible when the first detecting circuit detects the second given potential relation; and wherein the redundancy memory cell group is accessible when the third detecting circuit detects the first given potential relation, and the second main memory cell group is accessible when the third detecting circuit detects the second given potential relation.

Claim 93

A semiconductor memory device according to claim 85, wherein the first main memory cell group has a first main memory cell subgroup having a plurality of memory cells and a second main memory cell subgroup having a plurality of memory cells; wherein the second main memory cell group has a third main memory cell subgroup having a plurality of memory cells and a fourth main memory cell subgroup having a plurality of memory cells; wherein the second given potential relation has first and second states; wherein the first main memory cell subgroup is accessible when the first detecting circuit detects the second given potential relation and the third main memory cell subgroup is accessible when the third detecting circuit detects the second given potential relation if the second given potential relation is at the first state; and wherein the second main memory cell subgroup is accessible when the first detecting circuit detects the second given potential relation and the fourth main memory cell subgroup is accessible when the third detecting circuit detects the second given potential relation if the second given potential relation is at the second state.

Claim 94

A semiconductor memory device according to claim 86, wherein the redundancy memory cell group has a first redundancy memory cell subgroup having a plurality of memory cells and a second redundancy memory cell subgroup having a plurality of memory cells; wherein the third main memory cell subgroup is accessible when the first detecting circuit detects the first given potential relation and the first redundancy memory cell subgroup is accessible when the third detecting circuit detects the first given potential relation if the second given potential relation is at the first state; and wherein the fourth main memory cell subgroup is accessible when the first detecting circuit detects the first given potential relation and the second redundancy memory cell subgroup is accessible when the third detecting circuit detects the first given potential relation if the second given potential relation is at the second state.

Claim 95

A semiconductor memory device according to claim 87, wherein the first main memory cell subgroup is coupled to a first select line; wherein the second main memory cell subgroup is coupled to a second select line; wherein the third main memory cell subgroup is coupled to a third select line; wherein the fourth main memory cell subgroup is coupled to a fourth select line; wherein the first redundancy memory cell subgroup is coupled to a fifth select line; wherein the second redundancy memory cell subgroup is coupled to a sixth select line; wherein the first select line and the second select line are coupled to the first controlled circuit; wherein the third select line and the fourth select line are coupled to the second controlled circuit; wherein the fifth select line and the sixth select line are coupled to the third controlled circuit; wherein the first controlled circuit is responsive to the first control signal for activating the first select line when the first control signal is at the first potential level and activating the second select line when the first control signal is at the second potential level; wherein the second controlled circuit is responsive to the first control signal for activating the third select line when the first control signal is at the first potential level and activating the fourth select line when the first control signal is at the second potential level; wherein the third controlled circuit is responsive to the first control signal for activating the fifth select line when the first control signal is at the first potential level and activating the sixth select line when the first control signal is at the second potential level; wherein the drive circuit outputs the first control signal; and wherein the first terminal receives one of the first control signal and a signal representing the potential level substantially the same as that of the first control signal from the drive circuit.

Claim 96

A semiconductor memory device according to claim 88, wherein the first controlled circuit activates one of the first and second select lines in response to the second control signal and the first control signal; wherein the second controlled circuit activates one of the third and fourth select lines in response to the second control signal and the first control signal; and wherein the third controlled circuit activates one of the fifth and sixth select lines in response to the second control signal and the first control signal.

Claim 97

A semiconductor memory device according to claim 89, wherein the first, second and third controlled circuits are respectively responsive to a first, second and third select line activation circuit.

Claim 98

A semiconductor memory device according to claim 90, wherein the first given potential relation is that both the first and second nodes are substantially at the first potential level; and wherein the second given potential relation is that the second terminal is substantially at a second potential level when the first terminal is substantially at the first potential level, and the first terminal is substantially at the second potential level when the second terminal is substantially at the first potential level.

Claim 99

A semiconductor memory device according to claim 90, wherein the first given potential relation is that when one of the first and second nodes is substantially at the first potential level, one of the third and fourth nodes is substantially at the second potential level, respectively, and wherein the second given potential relation is that both the first and second terminals are substantially at the same potential level.

Claim 100

A semiconductor memory device according to claim 90, wherein the first to fourth conductive portions are fuse elements.

Claim 101

A semiconductor memory device according to claim 90, wherein the first and second control signals are address signals.

Claim 102

A semiconductor memory device according to claim 90, wherein each of the first to sixth select lines comprises a plurality of word lines; wherein the first select line activation circuit is responsive to the third control signal to thereby cause one word line of the first and second select lines to be active; wherein the second select line activation circuit is responsive to the third control signal to thereby cause one word line among the third and fourth select lines to be active; and wherein the third select line activation circuit is responsive to the third control signal to thereby cause one word line among the fifth and sixth select lines to be active.

Claim 103

A semiconductor memory device according to claim 95, wherein each of the first to sixth select lines is activated when one of the word lines which belong thereto is active.

Claim 104

A semiconductor memory device according to claim 82, wherein the first terminal receives one of the first control signal and a signal synchronous with the first control signal; wherein the first control signal is changed from the first potential level to, second potential level or is change from the second potential level to the first potential level; and wherein the second terminal receives a third control signal having the second given potential relation to the first control signal.

Claim 105

A semiconductor memory device according to claim 97, further including a second detecting circuit coupled to the first and second terminals for detecting that one of the first control signal and the signal synchronous with the first control signal and the third control signal have the second given potential relation; wherein the second detecting circuit applies a fourth control signal to the first and third detecting circuits after the lapse of a first given time from a time of detection; and wherein the first and third detecting circuits applies the second control signal to the second and third controlled circuits after receiving the fourth control signal.

Claim 106

A semiconductor memory device according to claim 98, wherein the third node receives the first control signal at the lapse of a second given time from a time that the first terminal received the first control signal if the first and third conductive portions are blown; and wherein the first given time is longer than the second given time.

Claim 107

A semiconductor memory device according to claim 99, wherein the second detecting circuit includes a delay circuit; and wherein the first given time is set by the delay circuit.

Claim 108

A semiconductor memory device according to claim 97, wherein the first terminal receives the first control signal through a first inverter circuit, wherein the second terminal receives the third control signal through a second inverter circuit, and wherein the drive circuit outputs the first and third control signals having the second given potential relation during an operating time and outputs the first and third control signals, both having the second potential level during a non-operating time.

Claim 109

A semiconductor memory device according to claim 101, wherein the first and second potential supply circuits cause the third and fourth nodes to be at the first potential level during the non-operating time.

Claim 110

A semiconductor memory device according to claim 102, further including a second detecting circuit coupled to the first and second terminals for detecting that one of the first control signal and the signal synchronous with the first control signal have the second given potential relation to the third control signal, wherein the second detecting circuit applies a fourth control signal to the first and third detecting circuit at the lapse of a first given time from a time of detection, and wherein the first and third detecting circuit applies the second control signal to the second and third controlled circuit after receiving the fourth control signal.

Claim 111

A semiconductor memory device according to claim 103, wherein the first node receives the first control signal at the lapse of a second given time from a time that the first terminal received the first control signal if the first conductive portion is blown; and wherein the first given time is longer than the second given time.

Claim 112

A semiconductor memory device according to claim 104, wherein the second detecting circuit includes a delay circuit, and wherein the first given time is set by the delay circuit.

Claim 113

A semiconductor memory device comprising: a first main select line group including a first select line group having a plurality of select lines and a second select line group having a plurality of select lines; a second main select line group including a third select line group having a plurality of select lines and a fourth select line group having a plurality of select lines; a redundancy select line group including a fifth select line group having a plurality of select lines and a sixth select line group having a plurality of select lines; a respective plurality of memory cells coupled to each of the select lines; a first select line activation circuit for activating one of the select lines of the first select line group in response to control signals including a first control signal, the first select line activation circuit activating one of the select lines of the first select line group when the first control signal is at a first potential level and activating one of the select lines of the second select line group when the first control signal is at a second potential level; a second select line activation circuit for activating one of the select lines of the second select line group in response to the control signals including the first control signal, the second select line activation circuit activating one of the select lines of the third select line group when the first control signal is at the first potential level and activating one of the select lines of the fourth select line group when the first control signal is at the second potential level; a third select line activation circuit for activating one of the select lines of the redundancy select line group in response to the control signals including the first control signal, the third select line activation circuit activating one of the select lines of the fifth select line group when the first control signal is at the first potential level and activating one of the select lines of the sixth select line group when the first control signal is at the second potential level; a first conductive line having a first terminal at one end thereof to receive the first control signal, a second terminal at the other end thereof, a first node and a second node connecting between the first and second terminals, a first conductive portion connecting between the first terminal and the first node and a second conductive portion connecting between the first node and the second node; a first potential holding circuit for causing nodes coupled to the second terminal to be at one of the first and second potential levels when one of the first and second conductive portions is blown; a second conductive line having a third terminal which is at the second potential level when the first control signal is at the first potential level and is at the first potential level when the first control signal is at the second potential level, the third terminal at one end of the second conductive line for receiving a second control signal, a fourth terminal at the other end thereof, third and fourth nodes connecting between the third and fourth terminals, a third conductive portion connecting between the third terminal and the third node and a fourth conductive portion connecting between the third node and the fourth node; a second potential holding circuit for causing the nodes coupled to the fourth terminal to be at one of the first and second potential levels when one of the third and fourth conductive portions is blown; first and second control signal generating circuits for outputting a third control signal of the control signals, wherein the first control signal generating circuit coupled to the first and third nodes enables the third control signal to be supplied to the second select line activation circuit when both of the first and third nodes are at one of the first and second potential levels, and enables the third control signal to be supplied to the first select line activation circuit when both of the first and third nodes are not at one of the first and second potential levels, and wherein the second control signal generating circuit is coupled to the second and fourth nodes and enables the third control signal to be supplied to the third select line activation circuit when both of the second and fourth nodes are at one of the first and second potential levels, and enables the third control signal to be supplied to the second select line activation circuit when both of the second and fourth nodes are not at one of the first and second potential levels.

Claim 114

A semiconductor memory device comprising: a first main select line group including a first select line group having a plurality of select lines and a second select line group having a plurality of select lines; a second main select line group including a third select line group having a plurality of select lines and a fourth select line group having a plurality of select lines; a redundancy select line group including a fifth select line group having a plurality of select lines and a sixth select line group having a plurality of select lines; a respective plurality of memory cells coupled to each of the select lines; a first select line activation circuit for activating one of the select lines of the first select line group in response to control signals including a first control signal, the first select line activation circuit activating one of the select lines of the first select line group when the first control signal is at a first potential level and activating one of the select lines of the second select line group when the first control signal is at a second potential level; a second select line activation circuit for activating one of the select lines of the second select line group in response to the control signals including the first control signal, the second select line activation circuit activating one of the select lines of the third select line group when the first control signal is at the first potential level and activating one of the select lines of the fourth select line group when the first control signal is at the second potential level; a third select line activation circuit for activating one of the select lines of the redundancy select line group in response to the control signals including the first control signal, the third select line activation circuit activating one of the select lines of the fifth select line group when the first control signal is at the first potential level and activating one of the select lines of the sixth select line group when the first control signal is at the second potential level; a first conductive line having a first terminal at one end thereof to receive the first control signal, a second terminal at the other end thereof, a first node and a second node connecting between the first and second terminals, a first conductive portion connecting between the first terminal and the first node and a second conductive portion connecting between the first node and the second node; a first potential holding circuit for causing nodes coupled to the second terminal to be at one of the first and second potential levels when one of the first and second conductive portions is blown; a second conductive line having a third terminal which is at the second potential level when the first control signal is at the first potential level and is at the first potential level when the first control signal is at the second potential level, the third terminal at one end of the second conductive line for receiving a second control signal, a fourth terminal at the other end thereof, third and fourth nodes connecting between the third and fourth terminals, a third conductive portion connecting between the third terminal and the third node and a fourth conductive portion connecting between the third node and the fourth node; a second potential holding circuit for causing the nodes coupled to the fourth terminal to be at one of the first and second potential levels when one of the third and fourth conductive portions is blown; first and second control signal generating circuits for outputting a third control signal of the control signals, wherein the first control signal generating circuit coupled to the first and third nodes enables the third control signal to be supplied to the second select line activation circuit when both of the first and third nodes are at one of the first and second potential levels, and enables the third control signal to be supplied to the first select line activation circuit when both of the first and third nodes are not at one of the first and second potential levels, and wherein the second control signal generating circuit is coupled to the second and fourth nodes and enables the third control signal to be supplied to the third select line activation circuit when both of the second and fourth nodes are at one of the first and second potential levels, and enables the third control signal to be supplied to the second select line activation circuit when both of the second and fourth nodes are not at one of the first and second potential levels.