US5394361A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read/write memory
Assignee: AT&T Inc
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Filing: 1992-10-22
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Granted: 1995-02-28
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Expires: 2012-10-22
Abstract
Abstract Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Reduced power consumption is achieved in such memories by preventing the occurrance of a write operation if the value of a bit to be written to a memory cell is the same as the value of the bit currently stored in that memory cell. More particularly, the result of a read operation on a particular memory cell is compared with the data value to be written to that cell to determine whether a subsequent write operation is required. If the value in the cell equals the value to be written, the write operation is not performed.
Inventors
- 👤 Alexander G. Dickinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:15
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/1051
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
87 words
Apparatus comprising: a random access memory Capable of reading from and writing to a memory cell of said memory in a single memory access cycle; means for comparing the value of a bit stored at said memory cell with the value of an input bit to be written to said memory cell; and means responsive to the comparing means for writing the input bit value to said memory cell only if the input bit value differs from the value of the bit stored at said memory cell.
Claim 2
Dependent Claim
87 words
Apparatus comprising: a random access memory Capable of reading from and writing to a memory cell of said memory in a single memory access cycle; means for comparing the value of a bit stored at said memory cell with the value of an input bit to be written to said memory cell; and means responsive to the comparing means for writing the input bit value to said memory cell only if the input bit value differs from the value of the bit stored at said memory cell.
Claim 3
Dependent Claim
12 words
The invention of claim 1 wherein comparing means comprises an exclusive-OR gate.
Claim 4
Dependent Claim
98 words
Apparatus comprising: a random access memory capable of reading from and writing to a memory cell of said memory in a single memory access cycle; means for comparing the value of a bit stored at said memory cell with the value of an input bit to be written to said memory cell said comparing means comprising an exclusive-OR gate: and means responsive to the comparing means for inhibiting writing of the input bit value to said memory cell when the input bit value and the value of the bit stored at said memory cell are substantially the same.
Claim 5
Dependent Claim
98 words
Apparatus comprising: a random access memory capable of reading from and writing to a memory cell of said memory in a single memory access cycle; means for comparing the value of a bit stored at said memory cell with the value of an input bit to be written to said memory cell said comparing means comprising an exclusive-OR gate: and means responsive to the comparing means for inhibiting writing of the input bit value to said memory cell when the input bit value and the value of the bit stored at said memory cell are substantially the same.
Claim 6
Independent Claim
87 words
A method for storing information in a random access memory, the method comprising the steps of: comparing the value of a bit stored in an individual memory cell of said memory, which can be read from and written to within a single memory access cycle, with the value of an input bit to be written to said memory cell; and writing the input bit value to said memory cell only if the input bit value differs from the value of the bit stored at said memory cell.
Claim 7
Independent Claim
87 words
A method for storing information in a random access memory, the method comprising the steps of: comparing the value of a bit stored in an individual memory cell of said memory, which can be read from and written to within a single memory access cycle, with the value of an input bit to be written to said memory cell; and writing the input bit value to said memory cell only if the input bit value differs from the value of the bit stored at said memory cell.
Claim 8
Dependent Claim
39 words
The invention of claim 4 wherein the comparing step comprises: reading the value of the stored bit from the memory cell; and applying to an exclusive-OR gate the value read from the memory cell and the input bit value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |