US5394351A
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US
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Optimized binary adder and comparator having an implicit constant for an input
Assignee: GlobalFoundries Inc
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Filing: 1994-03-11
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Granted: 1995-02-28
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Expires: 2014-03-11
Abstract
Abstract A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or a zero. The three-input comparator can be modified to be a three-input adder by using a full carry-propagate adder (CPA). By taking into account a priori restrictions on the possible input operands, these arithmetic circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.
Inventors
- 👤 Larry Widigen
- 👤 Elliot A. Sowadsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/02; G06F7/026
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
155 words
A binary arithmetic circuit for evaluating two binary variables (A and B) and a binary constant, said circuit comprising: a carry-save adder having sum and carry outputs, said carry-save adder including a constant-adder bit-cell, said constant-adder bit-cell having inputs A and B, a sum output, wherein the expanded sum-of-products form of said sum output is given by S(A,B)=Σ0,3, and a carry output, wherein the expanded sum-of-products form of said carry output is given by C(A,B)=Σ1,2,3, wherein said constant-adder bit-cell's sum and said carry output are included within said carry-save adder's sum and carry outputs, respectively, and wherein said constant-adder bit-cell is used in a bit position of said carry-save adder that corresponds to a bit value one in said binary constant; and a carry-propagation circuit having inputs coupled to at least some of said sum and carry outputs of said carry-save adder, and a carry output from the most significant bit of said carry-propagation circuit.
Claim 2
Dependent Claim
155 words
A binary arithmetic circuit for evaluating two binary variables (A and B) and a binary constant, said circuit comprising: a carry-save adder having sum and carry outputs, said carry-save adder including a constant-adder bit-cell, said constant-adder bit-cell having inputs A and B, a sum output, wherein the expanded sum-of-products form of said sum output is given by S(A,B)=Σ0,3, and a carry output, wherein the expanded sum-of-products form of said carry output is given by C(A,B)=Σ1,2,3, wherein said constant-adder bit-cell's sum and said carry output are included within said carry-save adder's sum and carry outputs, respectively, and wherein said constant-adder bit-cell is used in a bit position of said carry-save adder that corresponds to a bit value one in said binary constant; and a carry-propagation circuit having inputs coupled to at least some of said sum and carry outputs of said carry-save adder, and a carry output from the most significant bit of said carry-propagation circuit.
Claim 3
Dependent Claim
17 words
The binary arithmetic circuit of claim 1, wherein said binary constant is equal to 10 (decimal 2).
Claim 4
Dependent Claim
15 words
The binary arithmetic circuit of claim 1, wherein said carry-propagation circuit further has sum outputs.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |