US5394194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gain control circuit and gradation correcting apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1993-01-27
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Granted: 1995-02-28
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Expires: 2013-01-27
Abstract
Abstract A small scale gain control circuit for controlling gain correction quantity is realized, using the configuration of an inverter, a subtraction circuit, a limiter, and a multiplication circuit. Gain correction quantity is controlled in such a way that in the gradation correcting apparatus a first constant fixes a value beyond which gain correction quantity is zero and a second constant fixes an inclination of the characteristics line.
Inventors
- 👤 Yosuke Izawa
- 👤 Naoji Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:22
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
173 words
A gradation control circuit for processing an input image signal having a distribution histogram of brightness level, said gradation control circuit comprising: a gain control circuit comprising: (a) an inverter for inverting a gain control input signal to generate an inverted signal, said gain control input signal is a maximum value of the distribution histogram of brightness level, (b) means for subtracting a signal representative of a first constant from said inverted signal to generate a subtracted signal, (c) limiter means for generating (1) an output signal of zero value when said subtracted signal is less than zero, and (2) an output signal equal in value to said subtracted signal when said subtracted signal is not less than zero, (d) a multiplication circuit for multiplying said output signal by a second constant, means for generating a gradation correction signal by multiplying (1) a value determined from the distribution histogram of brightness level and (2) the output of the multiplication circuit, and means for adding said gradation correction signal to the input image signal.
Claim 2
Dependent Claim
173 words
A gradation control circuit for processing an input image signal having a distribution histogram of brightness level, said gradation control circuit comprising: a gain control circuit comprising: (a) an inverter for inverting a gain control input signal to generate an inverted signal, said gain control input signal is a maximum value of the distribution histogram of brightness level, (b) means for subtracting a signal representative of a first constant from said inverted signal to generate a subtracted signal, (c) limiter means for generating (1) an output signal of zero value when said subtracted signal is less than zero, and (2) an output signal equal in value to said subtracted signal when said subtracted signal is not less than zero, (d) a multiplication circuit for multiplying said output signal by a second constant, means for generating a gradation correction signal by multiplying (1) a value determined from the distribution histogram of brightness level and (2) the output of the multiplication circuit, and means for adding said gradation correction signal to the input image signal.
Claim 3
Dependent Claim
188 words
A gradation control circuit which controls the gradation of an input image signal by adding a gradation correction signal to an input image signal, said gradation control circuit comprising: means for generating a distribution histogram of brightness level of the input image signal, means for determining a temporary gradation correction signal from the distribution histogram of brightness level, a gain control circuit comprising: (a) an inverter which inverts a gain control input signal to produce an inverted signal, said gain control input signal is a maximum value of the distribution histogram of brightness level, (b) means for subtracting a first constant from said inverted signal, (c) limiter means for generating (1) an output signal of zero value when said subtracted output signal is less than zero, and (2) an output signal equal in value to said subtracted output signal when said subtracted output signal is not less than zero, and (d) a multiplication circuit for multiplying the output signal of the limiter by a second constant, and means for generating said gradation correction signal by multiplying the temporary gradation correction signal by the output of the multiplication circuit.
Claim 4
Dependent Claim
188 words
A gradation control circuit which controls the gradation of an input image signal by adding a gradation correction signal to an input image signal, said gradation control circuit comprising: means for generating a distribution histogram of brightness level of the input image signal, means for determining a temporary gradation correction signal from the distribution histogram of brightness level, a gain control circuit comprising: (a) an inverter which inverts a gain control input signal to produce an inverted signal, said gain control input signal is a maximum value of the distribution histogram of brightness level, (b) means for subtracting a first constant from said inverted signal, (c) limiter means for generating (1) an output signal of zero value when said subtracted output signal is less than zero, and (2) an output signal equal in value to said subtracted output signal when said subtracted output signal is not less than zero, and (d) a multiplication circuit for multiplying the output signal of the limiter by a second constant, and means for generating said gradation correction signal by multiplying the temporary gradation correction signal by the output of the multiplication circuit.
References Cited (Backward Citations)
US4187519A
Cited
JPS60192468A
Cited
US5048110A
Cited
US4797744A
Cited
US4771192A
Cited
JPS646589A
Cited
JPH01241988A
Cited
JPH0219070A
Cited
US5220427A
Cited
US5099330A
Cited
US5089891A
Cited
JPH048068A
Cited
JPH0423570A
Cited
JPH0445486A
Cited
JPH0447766A
Cited
JPH0477179A
Cited
US5294986A
Cited
US5315389A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |