US5394152A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Radar processing apparatus and method
Assignee: Massachusetts Institute of Technology
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Filing: 1993-08-02
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Granted: 1995-02-28
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Expires: 2013-08-02
Abstract
Abstract A radar processor comprises a multi-port memory device having memory which can be accessed by at least three ports. A first port receives input data from a data providing means. A second port couples a first processor which performs radar processing. A third port couples at least one second processor which assists the first processor by also performing radar processing. The multi-port memory device further includes an arbiter for coordinating and determining when each of the three ports can access the memory of the multi-port memory device. The first and second processors share information with each other via the multi-port memory device.
Inventors
- 👤 James V. Pieronek
- 👤 Jeffrey L. Gertz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:32
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/88; G01S13/91; G01S13/74; G01S13/76; G01S13/765; G01S13/767; G01S13/78; G01S13/781; G01S13/784; G01S13/86
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
A radar processor, comprising: a first multi-port memory device having memory which can be accessed by at least three ports, the device including a first port for receiving input radar data from a data providing means, a second port coupled to the input of an array signal processor which performs radar processing, a third port coupled to a first digital signal processor which performs radar processing, and an arbiter for coordinating and determining when each of the three ports can access the memory of the first multi-port memory device, wherein the array signal processor and the first digital signal processor communicating with each other via the first multi-port memory device, a second multi-port memory device having memory which can be accessed by at least three ports, the device including a first port coupled to the output of the array signal processor, a second port coupled to the input of a message interface processor which formats radar target and weather reports from processed radar data, a third port coupled to a second digital signal processor which performs radar processing, and an arbiter for coordinating and determining when each of the three ports can access the memory of the second multi-port memory device, wherein the array signal processor and the second digital signal processor communicate with each other via the second multi-port memory device, and the first and second digital signal processors communicate with each other via a separate interface between the first and second digital signal processors.
Claim 2
Dependent Claim
246 words
A radar processor, comprising: a first multi-port memory device having memory which can be accessed by at least three ports, the device including a first port for receiving input radar data from a data providing means, a second port coupled to the input of an array signal processor which performs radar processing, a third port coupled to a first digital signal processor which performs radar processing, and an arbiter for coordinating and determining when each of the three ports can access the memory of the first multi-port memory device, wherein the array signal processor and the first digital signal processor communicating with each other via the first multi-port memory device, a second multi-port memory device having memory which can be accessed by at least three ports, the device including a first port coupled to the output of the array signal processor, a second port coupled to the input of a message interface processor which formats radar target and weather reports from processed radar data, a third port coupled to a second digital signal processor which performs radar processing, and an arbiter for coordinating and determining when each of the three ports can access the memory of the second multi-port memory device, wherein the array signal processor and the second digital signal processor communicate with each other via the second multi-port memory device, and the first and second digital signal processors communicate with each other via a separate interface between the first and second digital signal processors.
Claim 3
Dependent Claim
43 words
The radar processor of claim 1 wherein the arbiter of the first multi-port memory provides highest priority for memory accesses to the array signal processor, second highest priority to the data providing means, and third highest priority to the first digital signal processor.
Claim 4
Dependent Claim
21 words
The radar processor of claim 1 wherein the input data comprises primary radar return data and beacon reply data from aircraft.
Claim 5
Dependent Claim
173 words
The radar processor of claim 1 wherein the first multi-port memory device, the second multi-port memory device, the array signal processor, the first digital signal processor, and the second digital signal processor cooperate to generate and store a report of beacon replies from aircraft by: creating a group having a plurality of beacon replies from radar targets which are represented by the input radar data; determining whether the group satisfies predetermined requirements including all beacon replies in the group being recognizable and all replies having a common beacon code; if the group does not satisfy the predetermined requirements, determining whether the group contains beacon replies which originate from two different aircraft, and then creating a report which matches each of the two aircraft to the corresponding replies; and if the group does not contain beacon replies originating from two different aircraft, determining whether all replies in the group originate from a single aircraft as represented by a single target track, and then generating a report which matches the single aircraft to the replies.
Claim 6
Dependent Claim
25 words
The radar processor of claim 4 wherein the radar processor also determines whether the report is due to a reflection of a beacon reply signal.
Claim 7
Dependent Claim
34 words
The radar processor of claim 5 wherein the radar processor also identifies the report as false if it is due to a reflection and as true if it is not due to a reflection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |