Power-on reset circuit including dual sense amplifiers

Claim 2

A power on reset circuit for an integrated circuit device, said power on reset circuit comprising: means for providing a first detect signal if a supply voltage exceeds a first specified value; a sense amplifier circuit powered by said supply voltage for indicating that sense amplifiers in said integrated circuit device will work properly, said sense amplifier circuit including: a first sense amplifier which provides a first amplifier output signal, a second sense amplifier which provides a second amplifier output signal, and a first logic gate for receiving said first and second amplifier output signals and providing a second detect signal; and a second logic gate for receiving said first and second detect signals and providing an output signal.

Claim 3

A power on reset circuit as in claim 1 where said first specified value is larger than the minimum value needed to operate logic gates in said integrated circuit device.

Claim 4

A power on reset circuit as in claim 1 further comprising: a Schmitt trigger responsive to said output signal, wherein said Schmitt trigger switches state at a higher voltage level if said output signal is rising and a lower voltage level if said output signal is falling.

Claim 5

A power on reset circuit as in claim 3 further comprising: delay means coupled between said first logic gate and said Schmitt trigger.

Claim 6

A power on reset circuit as in claim 4 wherein said delay means includes at least two inverters.

Claim 7

A power on reset circuit for an integrated circuit device having a plurality of sense amplifiers, said power on reset circuit comprising: means for providing a first detect signal if a first supply voltage exceeds a specified value; means for providing a second detect signal, wherein said means for providing a second detect signal receives a reference voltage which substantially matches the trigger points of said means for providing a second detect signal and said plurality of sense amplifiers in said integrated circuit device; and a first logic gate for receiving said first and second detect signals and providing an output signal; wherein said means for providing a first detect signal comprises: a first N-channel transistor and a first P-channel transistor connected in series between said first supply voltage and a second supply voltage; and a second P-channel transistor and a second N-channel transistor connected in series between said first supply voltage and said second supply voltage, said first detect signal being taken from a node between said second P-channel transistor and said second N-channel transistor, wherein the gates of said first and second N-channel transistors and said first and second P-channel transistors are commonly connected; wherein said first and second N-channel transistors have a threshold voltage Vtn, said first and second P-channel transistors have a threshold voltage Vtp, wherein said first detect signal is a logical high signal provided said first supply voltage is greater than Vtp+Vtn.

Claim 8

A power on reset circuit for an integrated circuit device having a plurality of sense amplifiers, said power on reset circuit comprising: means for providing a first detect signal if a first supply voltage exceeds a specified value; means for providing a second detect signal, wherein said means for providing a second detect signal receives a reference voltage which substantially matches the trigger points of said means for providing a second detect signal and said plurality of sense amplifiers in said integrated circuit device; and a first logic gate for receiving said first and second detect signals and providing an output signal; wherein said means for providing a first detect signal comprises: a first N-channel transistor and a first P-channel transistor connected in series between said first supply voltage and a second supply voltage; and a second P-channel transistor and a second N-channel transistor connected in series between said first supply voltage and said second supply voltage, said first detect signal being taken from a node between said second P-channel transistor and said second N-channel transistor, wherein the gates of said first and second N-channel transistors and said first and second P-channel transistors are commonly connected; wherein said first and second N-channel transistors have a threshold voltage Vtn, said first and second P-channel transistors have a threshold voltage Vtp, wherein said first detect signal is a logical high signal provided said first supply voltage is greater than Vtp+Vtn.

Claim 9

A power on reset circuit as in claim 6 further including a third N-channel transistor connected in series with said first N-channel transistor, wherein said first detect signal is a logical high signal provided said first supply voltage is greater than Vtp+2Vtn.

Claim 10

A power on reset circuit for an integrated circuit, said power on reset circuit comprising: means for providing a first detect signal if a supply voltage exceeds a specified value; means for providing a second detect signal; and a first logic gate for receiving said first and second detect signals and providing an output signal, wherein said means for providing a second detect signal comprises two sense amplifiers manufactured by the same process and with the same component sizes as sense amplifiers elsewhere in said integrated circuit, said sense amplifiers providing said second detect signal only if said supply voltage reaches a predetermined level.

Claim 11

A power on reset circuit for an integrated circuit, said power on reset circuit comprising: means for providing a first detect signal if a supply voltage exceeds a specified value; means for providing a second detect signal; and a first logic gate for receiving said first and second detect signals and providing an output signal, wherein said means for providing a second detect signal comprises two sense amplifiers manufactured by the same process and with the same component sizes as sense amplifiers elsewhere in said integrated circuit, said sense amplifiers providing said second detect signal only if said supply voltage reaches a predetermined level.

Claim 12

A power on reset circuit as in claim 8 in which said two amplifiers comprise: a first sense amplifier which generates a logical 1 output signal if said supply voltage reaches said predetermined level; and a second sense amplifier which generates a logical 0 output signal if said supply voltage reaches said predetermined level; and wherein said means for providing a second detect signal comprises: sense amplifier gating means which provides said second detect signal in response to a combination of said logical 1 from said first sense amplifier and said logical 0 from said second sense amplifier.

Claim 13

A power on reset circuit for an integrated circuit device, said power on reset circuit comprising: means for providing a first detect signal if a first supply voltage exceeds a specified value; means for providing a second detect signal, wherein said means for providing a second detect signal has a trigger point which matches the trigger point of at least one sense amplifier in said integrated circuit device; a first logic gate for receiving said first and second detect signals; a Schmitt trigger responsive to an output signal provided by said first logic gate, wherein said Schmitt trigger switches state at a higher voltage level if said output signal is rising and a lower voltage level if said output signal is falling; and delay means coupled between said first logic gate and said Schmitt trigger, wherein said delay means includes: a first inverter and a second inverter connected in series between said first logic gate and said Schmitt trigger; and a first capacitor and a second capacitor, said first capacitor connected to a node between said first and second inverters, said second capacitor connected between a node between said second inverter and said Schmitt trigger.

Claim 14

A power on reset circuit for an integrated circuit device, said power on reset circuit comprising: means for providing a first detect signal if a first supply voltage exceeds a specified value; means for providing a second detect signal, wherein said means for providing a second detect signal has a trigger point which matches the trigger point of at least one sense amplifier in said integrated circuit device; a first logic gate for receiving said first and second detect signals; a Schmitt trigger responsive to an output signal provided by said first logic gate, wherein said Schmitt trigger switches state at a higher voltage level if said output signal is rising and a lower voltage level if said output signal is falling; and delay means coupled between said first logic gate and said Schmitt trigger, wherein said delay means includes: a first inverter and a second inverter connected in series between said first logic gate and said Schmitt trigger; and a first capacitor and a second capacitor, said first capacitor connected to a node between said first and second inverters, said second capacitor connected between a node between said second inverter and said Schmitt trigger.

Claim 15

A power on reset circuit for an integrated circuit device, said power on reset circuit comprising: means for providing a first detect signal if a first supply voltage exceeds a specified value; means for providing a second detect signal; a first logic gate for receiving said first and second detect signals; means for providing a third detect signal if said voltage supply exceeds a second specified value; and a second logic gate for receiving an output signal from said first logic gate and an output signal from said means for providing a third detect signal and providing an output signal.

Claim 16

A power on reset circuit for an integrated circuit device, said power on reset circuit comprising: means for providing a first detect signal if a first supply voltage exceeds a specified value; means for providing a second detect signal; a first logic gate for receiving said first and second detect signals; means for providing a third detect signal if said voltage supply exceeds a second specified value; and a second logic gate for receiving an output signal from said first logic gate and an output signal from said means for providing a third detect signal and providing an output signal.

Claim 17

A power on reset circuit as in Claim 11 in which said first and second specified values are equal.

Claim 18

A power on reset circuit as in claim 12 wherein said means for providing a first detect signal includes a plurality of N-channel transistors and a plurality of P-channel transistors, wherein said first and second specified values are Vtp+2Vtn where Vtn is the threshold voltage of each of said plurality of N-channel transistors and Vtp is the threshold voltage of each of said plurality of P-channel transistors.

Claim 19

A power on reset circuit as in claim 11 wherein said means for providing a third detect signal includes means for delaying said third detect signal if said supply voltage value exceeds said second specified value.

Claim 20

A power on reset circuit as in claim 11 wherein said means for providing a third detect signal comprises: means for generating a first stage output signal no greater than a first predetermined value; and means for supplying said third detect signal if said supply voltage exceeds said first stage output signal by a second predetermined value.

Claim 21

A power reset circuit as in claim 1 further comprising a reset device, wherein said second logic gate receives an output signal from said reset device.