US5392879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic failure detection system
Assignee: Otis Elevator Co
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Filing: 1993-04-16
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Granted: 1995-02-28
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Expires: 2013-04-16
Abstract
Abstract An electronic failure detector includes an electronic processor having processor inputs and processor outputs, a memory connected to one of the inputs, a logic circuit having logic circuit inputs and logic circuit outputs, the logic circuit inputs and logic circuit outputs being connected to others of the processor inputs, and instructions, stored within the non-volatile memory, for causing the processor to perform a logic check of the logic circuit and to generate a first signal on the processor output if said logic check is true, and to generate a second signal on the processor output if said logic check is false.
Inventors
- 👤 Robert C. Boyce
- 👤 Michael A. Spaner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:43
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
192 words
A detector, comprising: an electronic processor having processor inputs and processor outputs; a non-volatile memory connected to one of said processor inputs; a logic circuit having logic circuit inputs and logic circuit outputs, said logic circuit inputs and said logic circuit outputs being connected to others of said processor inputs; an and gate having gate inputs, and a gate output, one of said gate inputs being connected to one of said logic circuit outputs, another of said gate inputs being connected to one of said processor outputs; an electronic switch having switch inputs and a switch output, one of said switch inputs being connected to said gate output, another of said switch inputs being connected to another of said processor outputs, said switch output being connected to another of said processor inputs; and instructions, stored within said non-volatile memory, for causing said processor to perform a logic check of said logic circuit and to generate a first signal on said processor outputs if said logic check is true, and to generate a second signal on said processor outputs if said logic check is false, said first signal differing from said second signal.
Claim 2
Dependent Claim
192 words
A detector, comprising: an electronic processor having processor inputs and processor outputs; a non-volatile memory connected to one of said processor inputs; a logic circuit having logic circuit inputs and logic circuit outputs, said logic circuit inputs and said logic circuit outputs being connected to others of said processor inputs; an and gate having gate inputs, and a gate output, one of said gate inputs being connected to one of said logic circuit outputs, another of said gate inputs being connected to one of said processor outputs; an electronic switch having switch inputs and a switch output, one of said switch inputs being connected to said gate output, another of said switch inputs being connected to another of said processor outputs, said switch output being connected to another of said processor inputs; and instructions, stored within said non-volatile memory, for causing said processor to perform a logic check of said logic circuit and to generate a first signal on said processor outputs if said logic check is true, and to generate a second signal on said processor outputs if said logic check is false, said first signal differing from said second signal.
Claim 3
Dependent Claim
81 words
A detector as claimed in claim 1, wherein said logic check includes instructions for reading actual values of signals on said logic circuit inputs, for determining a plurality of calculated values for signals on said logic circuit outputs, for reading actual values of signals on said logic circuit outputs, for comparing the calculated values against the actual values of said logic circuit outputs, and for causing generation of said first signal if said calculated values are equal to said actual values.
Claim 4
Dependent Claim
61 words
A detector as claimed in claim 2, wherein said instructions for determining said plurality of calculated values include instructions for determining said calculated values according to the equations: F=A+B, H=F*C, G=C*E*D, I=H+G, wherein A, B, C, D and E are input signals on said logic circuit inputs and F, G, H and I are output signals on said logic circuit outputs.
Claim 5
Dependent Claim
21 words
A detector as claimed in claim 3, wherein said signal A is an input signal from an elevator door zone sensor.
Claim 6
Dependent Claim
21 words
A detector as claimed in claim 4, wherein said signal B is an input signal from an elevator door zone sensor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |