Method and apparatus for deskewing/resynchronizing data slices with variable skews

Claim 2

In a digital system comprising a plurality of data sending high speed circuits, and a data receiving high speed circuit, wherein each of said data sending high speed circuits concurrently generates and sends a stream of data slices and a companion stream of clock pulses to said data receiving high speed circuit, and said streams of data slices and clock pulses incur varying amount of delays when they travel from said data sending high speed circuits to said data receiving high speed circuit, an apparatus for deskewing/resynchronizing said streams of data slices, said apparatus comprising: a) buffer means coupled to said data sending high speed circuits for receiving said streams of data slices, and individually buffering said received streams of data slices for at most a time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices; b) sync pulse generation means for synchronously generating a plurality of streams of periodic sync pulses corresponding to said streams of data slices and clock pulses, each stream of periodic sync pulses having a predetermined periodicity p, said streams of periodic sync pulses incurring similar amount of delays as their corresponding streams of data slices and clock pulses when they travel to said data receiving high speed circuit; c) write buffer address generation means coupled to said data sending high speed circuits, said buffer means and said sync pulse generation means, for receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said buffer means using said received clock pulses and periodic sync pulses; and d) read buffer address generation means coupled to said data sending high speed circuits, said sync pulse generation means, and said buffer means for receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said buffer means using said received stream of clock pulses and periodic sync pulses.

Claim 3

The apparatus as set forth in claim 1, wherein, said buffer means comprises a plurality of circular buffer chains coupled to said data sending high speed circuits, said write buffer address generation means and said read buffer address generation means, for receiving and buffering said streams of data slices, each of said circular buffer chains having sufficient capacity for buffering one of said received streams of data slices for at most said time period t.

Claim 4

The apparatus as set forth in claim 2, wherein, each set of said corresponding data slices is read as soon as its data slices have been buffered in said circular buffer chains; said time period t equals the sum of the maximum skew between any two streams of data slices and the amount of set up and propagation time required to concurrently read a set of corresponding data slices from said circular buffer chains.

Claim 5

The apparatus as set forth in claim 3, wherein, each of said circular buffer chains has a capacity that is twice the capacity for buffering one of said received streams of data slices for at most said time period t.

Claim 6

The apparatus as set forth in claim 1, wherein, said sync pulse generation means comprises a plurality of sync pulse generation circuits coupled to said write buffer address generation means and said read buffer address generation means for synchronously generating said streams of periodic sync pulses with said predetermined periodicity p.

Claim 7

The apparatus as set forth in claim 5, wherein, each of said sync pulse generation circuits comprises a multi-state state machine and a set of flip-flops coupled to said multi-state state machine for synchronously generating one stream of periodic sync pulses with said predetermined periodicity p using a control value.

Claim 8

The apparatus as set forth in claim 1, wherein, said write buffer address generation means comprises a plurality of write buffer address generators coupled to said data sending high speed circuits, said buffer means, and said sync pulse generation means for receiving said streams of clock pulses and periodic sync pulses, and independently generating said write buffer addresses using said received streams of clock pulses and periodic sync pulses.

Claim 9

The apparatus as set forth in claim 1, wherein, said read buffer address generation means comprises: a delay pipe coupled said sync pulse generation means for receiving one of said streams of periodic sync pulses, applying a constant delay to said received stream of periodic sync pulses, said constant delay being logically equivalent to a constant storage location set back; and a read buffer address generator coupled to said data sending high speed circuits, said buffer means and said delay pipe, for receiving said corresponding stream of clock pulses of said received stream of periodic sync pulses and said delayed stream of periodic sync pulses, and generating said synchronized read buffer addresses using said received streams of clock pulses and delayed periodic sync pulses.

Claim 10

The apparatus as set forth in claim 8, wherein, said buffer means comprises a plurality of circular buffer chains coupled to said data sending high speed circuits, said write buffer address generation means and said read buffer address generation means, for receiving and buffering said streams of data slices, each of said circular buffer chains having sufficient capacity for buffering one of said received streams of data slices for at most said time period t; and said constant storage location set back equals one-half of said circular buffer chains' individual capacity.

Claim 11

The apparatus as set forth in claim 8, wherein, said received streams of data slices and periodic sync pulses are the streams incurring the most delays; and said constant storage location set back equals one storage location.

Claim 12

The apparatus as set forth in claim 8, wherein, said read buffer address generation means receives all of said streams of clock pulses and their corresponding streams of periodic sync pulses, instead of only one of said streams clock pulses and its corresponding stream of periodic sync pulses; said read buffer address generation means further comprises at least one selector coupled to said data sending high speed circuits and said sync pulse generation means for receiving said streams of clock pulses and their corresponding periodic sync pulses, and selecting one of said streams of clock pulses and its corresponding stream of periodic sync pulses, said delay pipe and said read buffer address generator being coupled to said data sending high speed circuits through said at least one selector.

Claim 13

The apparatus as set forth in claim 1, wherein, said sync pulse generation means are disposed on said data sending high speed circuit; and said buffer means, said write buffer address generation means and said read buffer address generation means, are disposed on said data receiving high speed circuit.

Claim 14

In a digital system comprising a plurality of data sending high speed circuits, and a data receiving high speed circuit, w herein each of said data sending high speed circuits concurrently generates and sends a stream of data slices and a common stream of clock pulses to said data receiving high speed circuit, and said streams of data slices and clock pulses incur varying amount of delays when they travel from said data sending high speed circuits to said data receiving high speed circuit, a method for deskewing/resynchronizing said streams of data slices, said method comprising the steps of: a) receiving said streams of data slices, and individually buffering said received streams of data slices for at most a first time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices; b) synchronously generating a plurality of streams of periodic sync pulses corresponding to said streams of data slices and clock pulses, each stream having a predetermined periodicity p, said streams of periodic sync pulses incurring similar amount of delays as their corresponding streams of data slices and clock pulses when they travel to said data receiving high speed circuit; c) receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said buffer means using said received clock pulses and sync pulses; and d) receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said buffer means using said received streams of clock pulses and periodic sync pulses.

Claim 15

In a digital system comprising a plurality of data sending high speed circuits, and a data receiving high speed circuit, w herein each of said data sending high speed circuits concurrently generates and sends a stream of data slices and a common stream of clock pulses to said data receiving high speed circuit, and said streams of data slices and clock pulses incur varying amount of delays when they travel from said data sending high speed circuits to said data receiving high speed circuit, a method for deskewing/resynchronizing said streams of data slices, said method comprising the steps of: a) receiving said streams of data slices, and individually buffering said received streams of data slices for at most a first time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices; b) synchronously generating a plurality of streams of periodic sync pulses corresponding to said streams of data slices and clock pulses, each stream having a predetermined periodicity p, said streams of periodic sync pulses incurring similar amount of delays as their corresponding streams of data slices and clock pulses when they travel to said data receiving high speed circuit; c) receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said buffer means using said received clock pulses and sync pulses; and d) receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said buffer means using said received streams of clock pulses and periodic sync pulses.

Claim 16

The method as set forth in claim 13, wherein, said step a) comprises receiving and buffering said streams of data slices in a plurality of circular buffer chains, each of said circular buffer chains having sufficient capacity for buffering one of said received streams of data slices for at most said time period t.

Claim 17

The method as set forth in claim 14, wherein, each set of corresponding slices is read as soon as its data slices have been buffered in said circular buffer chains; said time period t equals the sum of the maximum skew between any two streams of data slices and the amount of set up and propagation time required to concurrently read a set of corresponding data slices from said circular buffer chains.

Claim 18

The method as set forth in claim 15, wherein, each of said circular buffer chains has a capacity that is twice the capacity for buffering one of said received streams of data slices for at most said time period t.

Claim 19

The method as set forth in claim 13, wherein, said step b) comprises synchronously generating said streams of periodic sync pulses with said predetermined periodicity p using a plurality sync pulse generation circuits.

Claim 20

The method as set forth in claim 17, wherein, each of said sync pulse generation circuits comprises a multi-state state machine and a set of flip-flops coupled to said multi-state state machine for synchronously generating one of said streams of periodic sync pulses with said predetermined periodicity p using a control value.

Claim 21

The method as set forth in claim 13, wherein, said step c) comprises receiving said streams of clock pulses and periodic sync pulses, and independently generating said write buffer addresses using said received streams of clock pulses and periodic sync pulses by a plurality of write buffer address generators.

Claim 22

The method as set forth in claim 13, wherein, said step d) comprises: d.1) receiving one of said streams of periodic sync pulses, applying a constant delay to said received stream of periodic sync pulses, said constant delay being logically equivalent to a constant storage location set back; and d.2) receiving said received stream of periodic sync pulses' corresponding stream of clock pulses and said delayed stream of periodic sync pulses, and generating said synchronized read buffer addresses using said received stream of clock pulses and delayed periodic sync pulses by a read buffer address generator.

Claim 23

The method as set forth in claim 20, wherein, said step a) comprises receiving and buffering said streams of data slices in a plurality of circular buffer chains, each of said circular buffer chains having sufficient capacity for buffering one of said received streams of data slices for at most said time period t, each set of said corresponding data slices being read as soon as its data slices have been buffered in said circular buffer chains; and said constant storage location set back equals one-half of said circular buffer chains' individual capacity.

Claim 24

The method as set forth in claim 20, wherein, said received streams of data slice and periodic sync pulses are the streams incurring the most delays; and said constant storage location set back equals one storage location.

Claim 25

The method as set forth in claim 20, wherein, said step d.1) comprises receiving all of said streams of clock pulses and their corresponding streams of periodic sync pulses, instead of one of said streams of clock pulses and its corresponding stream of periodic sync pulses, and said step d.1) further comprises selecting one of said received streams of clock pulses and its corresponding stream of periodic sync pulses, said selected stream periodic sync pulses being applied said constant delay.

Claim 26

The method as set forth in claim 13, wherein, said sync pulse generation means are disposed on said data sending high speed circuit; and said buffer means, said write buffer address generation means, and said read buffer address generation means are disposed on said data receiving high speed circuit.

Claim 27

In a digital system comprising a plurality of data sending high speed circuits, and a data receiving high speed circuit, wherein each of said data sending high speed circuits concurrently generates and sends a stream of data slices and a companion stream of clock pulses to said data receiving high speed circuit, and said streams of data slices and clock pulses incur varying amount of delays when they travel from said data sending high speed circuits to said data receiving high speed circuit, an apparatus for deskewing/resynchronizing said streams of data slices, said apparatus comprising: a) a plurality of circular buffer chains of sufficient capacity coupled to said data sending high speed circuits for individually receiving and buffering one of said streams of data slices for at most a time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices; b) a plurality of sync pulse generation circuits for synchronously generating a plurality of streams of periodic sync pulses corresponding to said streams of data slices and clock pulses, each of said streams of periodic sync pulses having a predetermined periodicity p, said streams of periodic sync pulses incurring similar amount of delays as their corresponding streams of data slices and clock pulses when they travel to said data receiving high speed circuit; c) a plurality of write buffer address generators coupled to said data sending high speed circuits, said plurality of circular buffer chains and said sync pulse generation circuits, for receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said circular buffer chains using said received clock pulses and sync pulses; and d) read buffer address generators coupled to said data sending high speed circuits, said sync pulse generation circuits and said circular buffer chains, for receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said circular buffer chains using said received streams of clock pulses and periodic sync pulses.

Claim 28

In a digital system comprising a plurality of data sending high speed circuits, and a data receiving high speed circuit, wherein each of said data sending high speed circuits concurrently generates and sends a stream of data slices and a companion stream of clock pulses to said data receiving high speed circuit, and said streams of data slices and clock pulses incur varying amount of delays when they travel from said data sending high speed circuits to said data receiving high speed circuit, an apparatus for deskewing/resynchronizing said streams of data slices, said apparatus comprising: a) a plurality of circular buffer chains of sufficient capacity coupled to said data sending high speed circuits for individually receiving and buffering one of said streams of data slices for at most a time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices; b) a plurality of sync pulse generation circuits for synchronously generating a plurality of streams of periodic sync pulses corresponding to said streams of data slices and clock pulses, each of said streams of periodic sync pulses having a predetermined periodicity p, said streams of periodic sync pulses incurring similar amount of delays as their corresponding streams of data slices and clock pulses when they travel to said data receiving high speed circuit; c) a plurality of write buffer address generators coupled to said data sending high speed circuits, said plurality of circular buffer chains and said sync pulse generation circuits, for receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said circular buffer chains using said received clock pulses and sync pulses; and d) read buffer address generators coupled to said data sending high speed circuits, said sync pulse generation circuits and said circular buffer chains, for receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said circular buffer chains using said received streams of clock pulses and periodic sync pulses.

Claim 29

The apparatus as set forth in claim 25, wherein, each set of said corresponding data slices is read as soon as its data slices have been buffered in said circular buffer chains; and said time period t equals the sum of the maximum skew between any two streams of data slices and the amount of set up and propagation time required to concurrently read a set of corresponding data slices from said circular buffer chains, each set of corresponding slices being read as soon as its data slices have been buffered in said circular buffer chains.

Claim 30

The apparatus as set forth in claim 25, wherein, each of said circular buffer chains has a capacity that is twice the capacity for buffering one of said received streams of data slices for said first time period t.

Claim 31

The apparatus as set forth in claim 25, wherein, each of said sync pulse generation circuits comprises a multi-state state machine and a set of flip-flops coupled to said multi-state state machine for synchronously generating one stream of periodic sync pulses with said predetermined periodicity p using a control value.

Claim 32

The apparatus as set forth in claim 25, wherein, said read buffer address generator comprises: a delay pipe coupled said sync pulse generation circuits for receiving one of said streams of periodic sync pulses, applying a constant delay to said received stream of periodic sync pulses, said constant delay being logically equivalent to a constant storage location set back; and a read buffer address generator coupled to said data sending high speed circuits, said buffer means and said delay pipe, for receiving said corresponding stream of clock pulses of said received stream of periodic sync pulses and said delayed stream of periodic sync pulses, and generating said synchronized read buffer addresses using said received streams of clock pulses and delayed periodic sync pulses.

Claim 33

The apparatus as set forth in claim 29, wherein, said constant storage location set back equals one-half of said circular buffer chains' individual capacity.

Claim 34

The apparatus as set forth in claim 29, wherein, said received streams of data slice and periodic sync pulses are the streams incurring the most delays; and said constant storage location set back equals one storage location.

Claim 35

The apparatus as set forth in claim 25, wherein, said read buffer address generator receives all of said streams of clock pulses and their corresponding streams of periodic sync pulses, instead of one of said streams of clock pulses and its corresponding stream of periodic sync pulses; said read buffer address generator further comprises at least one selector, coupled to said data sending high speed circuits and said sync pulse generation circuits, for receiving said streams of clock pulses and their corresponding periodic sync pulses, and selecting one of said streams of clock pulses and its corresponding stream of periodic sync pulses, said delay pipe and said read buffer address generator being coupled to said data sending high speed circuits through said at least one selector.

Claim 36

The apparatus as set forth in claim 25, wherein, said sync pulse generation circuits are disposed on said data sending high speed circuits, one sync pulse generation circuit per data sending high speed circuit; and said circular buffer chains, said write address generators and said read address generator, are disposed on said data receiving high speed circuit.

Claim 37

The apparatus as set forth in claim 25, wherein, said digital system is a data instrumentation system; said data sending high speed circuits are data sending high speed probes; and said data receiving high speed circuit is a data receiving high speed trace control circuit.

Claim 38

A data instrumentation system comprising: a) a plurality of data sending high speed probes, each of said data sending high speed probes comprising means for generating a stream of data slices, a stream of clock pulses, and a stream of periodic sync pulses with a predetermined periodicity p; b) a data receiving high speed trace control circuit comprising: b.1) a plurality of circular buffer chains coupled to said data sending high speed probes for individually receiving and buffering one of said streams of data slices for at most a time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices, said streams of data slices incurring varying amount of delays when they travel from said data sending high speed probes to said circular buffer chains, b.2) a plurality of write buffer address generators coupled to said data sending high speed probes and said plurality of circular buffer chains for receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said circular buffer chains using said received clock pulses and periodic sync pulses, said streams of clock pulses and periodic sync pulses incurring similar varying amount of delays as they travel from said data sending high speed probes to said write buffer address generators, and b.3) read buffer address generators coupled to said data sending high speed probes and said circular buffer chains for receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said circular buffer chains using said received streams of clock pulses and periodic sync pulses.

Claim 39

A data instrumentation system comprising: a) a plurality of data sending high speed probes, each of said data sending high speed probes comprising means for generating a stream of data slices, a stream of clock pulses, and a stream of periodic sync pulses with a predetermined periodicity p; b) a data receiving high speed trace control circuit comprising: b.1) a plurality of circular buffer chains coupled to said data sending high speed probes for individually receiving and buffering one of said streams of data slices for at most a time period t, where t is a function of the maximum amount of skew between any two of said streams of data slices, said streams of data slices incurring varying amount of delays when they travel from said data sending high speed probes to said circular buffer chains, b.2) a plurality of write buffer address generators coupled to said data sending high speed probes and said plurality of circular buffer chains for receiving said streams of clock pulses and periodic sync pulses, and independently generating write buffer addresses for said circular buffer chains using said received clock pulses and periodic sync pulses, said streams of clock pulses and periodic sync pulses incurring similar varying amount of delays as they travel from said data sending high speed probes to said write buffer address generators, and b.3) read buffer address generators coupled to said data sending high speed probes and said circular buffer chains for receiving one of said streams of clock pulses and its corresponding periodic sync pulses, and generating synchronized read buffer addresses for said circular buffer chains using said received streams of clock pulses and periodic sync pulses.