Magnetic head circuit having a write current changeover circuit with a clamp voltage depending on write current for high-speed data transfer

Claim 2

A magnetic head circuit having a plurality of head circuit sets for a plurality of magnetic heads, each of said head circuit sets comprising: a first pair of transistors whose emitters are connected to each other for receiving data signals; first and second resistors each connected between a power source and a collector of a respective one of said first pair of transistors; a second pair of emitter follower transistors whose bases are connected to the collectors of said first pair of transistors for performing a differential operation; a third pair of differential transistors connected to said second pair of emitter follower transistors and whose emitters are connected to each other for performing a differential operation; a first current source connected to the emitters of said first pair of transistors for supplying a current to said first pair of transistors and said resistors connected to the first pair of transistors, said first current source including a first transistor having a first emitter-resistor, a first base and a first collector connected to the emitters of said first pair of transistors and having a predetermined emitter size ratio; a second current source connected to the emitters of said third pair of differential transistors, said second current source including a second transistor having a second emitter-resistor, a second base and a second collector connected to the emitters of said third pair of transistors and having substantially said predetermined emitter size ratio; a predetermined control voltage terminal connected to said first and second bases of said first and second current sources for receiving an adjustable control signal corresponding to inner/outer peripheries of a recording track; and a pair of signal terminals connected respectively to junction points between said second pair of emitter follower transistors and said third pair of transistors for outputting therefrom signals corresponding to said data signals, wherein collector voltages of said first pair of transistors are dependent on a current flowing through said first current source in response to said adjustable control signal.

Claim 3

A magnetic head circuit as set forth in claim 1, wherein said first and second current sources are transistors having a common base connected to said predetermined control voltage terminal applied with a constant adjustable voltage and each of which causes a current corresponding to currents flowing through said pair of signal terminals and said size ratio.

Claim 4

A magnetic head circuit as set forth in claim 1, further comprising another current source connected to the emitters of said first pair of transistors for providing differential operation of said first pair of transistors on the basis of said second predetermined voltage and for supplying a current to said first pair of transistors and said resistors connected to the collectors of said first pair of transistors.

Claim 5

A magnetic head circuit as set forth in claim 1, further comprising two frequency divider means for dividing the frequency of the data signals, and wherein each of said head circuit sets further comprises selection means for selecting one of outputs of said two frequency divider means according to selection signals and for providing the selected output to the bases of said first pair of transistors, and at least two of said head circuit sets receive different selection signals and at the same time provide signals corresponding to the data signals to the corresponding signal terminals.

Claim 6

A magnetic head circuit as set forth in claim 1, further comprising: first and second two-input differential operation means connected respectively to current sources, said first and second differential operation means each having capacitor means connected thereto for delaying differential operation; other differential operation means connected to one input of each of said differential operation means for detecting a level difference between data signals; wiring means connecting said pair of signal terminals to the other inputs of each of said differential operation means; and flip-flop means connected to said other differential operation means and a reset signal RS, said flip-flop means including a plurality of transistors.

Claim 7

A magnetic head circuit as set forth in claim 1, further comprising: first and second two-input differential operation means connected respectively to current sources; a predetermined reference voltage level connected to one input of each of said differential operation means; wiring means connecting said pair of signal terminals to the other input of each of said differential operation means; and timer means connected to said first and second differential operation means and including a capacitor and a current source, charges accumulated in said capacitor through said current source being discharged through differential operation of said first and second differential operation means according to voltage changes of said pair of signal terminals.

Claim 8

A magnetic head circuit as set forth in claim 1, further comprising frequency divider means connected to the bases of said first pair of transistors for dividing the frequency of the data signals.

Claim 9

A magnetic head circuit as set forth in claim 7, further comprising a detector circuit connected to said frequency divider means and said pair of signal terminals for providing a timing difference between the output signals of said pair of signal terminals representing a detection of one of an undesirable short circuit and an undesirable open circuit, and a latch circuit for receiving said timing difference for latching.

Claim 10

A magnetic head circuit as set forth in claim 1, further comprising a fourth pair of transistors whose emitters are connected to each other, whose collectors are connected with resistors and which receive at their bases said data signals, level shift means whose inputs are connected to the collector of said fourth pair of transistors and which provides voltage signals shifted with respect to signals provided from the collectors of said first pair of transistors to the bases of said second pair of emitter follower transistors, and connection means for providing outputs of said level shift means to the bases of said third pair of transistors.

Claim 11

A magnetic head circuit as set forth in claim 9, further comprising a third current source connected to the emitters of said fourth pair of transistors for providing differential operation of said fourth pair of transistors on the basis of said predetermined voltage, and a fourth current source connected to the emitters of said fourth pair of transistors for providing differential operation of said fourth pair of transistors on the basis of a second predetermined voltage.

Claim 12

A magnetic head circuit as set forth in claim 9, further comprising capacitor means connected to the inputs of said level shift means.

Claim 13

A magnetic head circuit as set forth in claim 1, further comprising two transistors whose emitters are connected to the bases of said second pair of emitter follower transistors, a common connection current source connected commonly to bases of said two transistors, and a resistor connected between said current source and a power source, wherein a current flowing through said resistor and said common connection current source determines a voltage at said bases of said second pair of emitter follower transistors in response to said adjustable control signal.

Claim 14

A magnetic head circuit as set forth in claim 12, wherein said common connection current source is connected to said predetermined control voltage terminal to cause a voltage corresponding to a differential operation current flowing through said second pair of emitter follower transistors to appear at said resistor, and further comprising yet another current source connected to the common bases of said two transistors to be driven on the basis of said another predetermined voltage.

Claim 15

A magnetic head circuit as set forth in claim 1, further comprising: a fourth pair of differential transistors whose bases are connected respectively to said pair of signal terminals and whose emitters are connected directly to each other to be operated according to a voltage appearing between said pair of signal terminals; a current source connected to the emitters of said fourth pair of differential transistors; first amplification transistors connected to the collectors of said fourth pair of differential transistors respectively; post-amplifiers connected respectively to outputs of said first amplification transistors; and wires relatively long when compared with a circuit scale and connected between said first amplification transistors and said post-amplifiers.

Claim 16

A magnetic head circuit as set forth in claim 14, further comprising: another pair of differential transistors connected to said post-amplifiers and whose emitters are connected to each other; a current source transistor connected to the bases of said pair of differential transistors; and a switching transistor connected to the collectors of said pair of differential transistors for receiving at their bases a control signal to control the differential operation current.

Claim 17

A magnetic head circuit for magnetic head signals comprising: a plurality of pairs of signal terminals; a plurality of pre-amplification circuits connected respectively to said plurality of pairs of signal terminals, each of said plurality of pre-amplification circuits includes: a pair of differential transistors whose bases are connected to associated one of said pairs of signal terminals and whose emitters are connected directly to each other and which are operated according to a voltage appearing between said pair of signal terminals; first and second amplification transistors whose emitters are connected to one collector of said pair of differential transistors; third and fourth amplification transistors whose emitters are connected to the other collector of another collector of said pair of differential transistors receiving at their bases a first selection signal, said second and fourth amplification transistors receiving at their bases a second selection signal; first diodes connected to the emitters and the bases of said first and said third amplification transistors, respectively; a current source connected to the emitters of said pair of differential transistors, and second diodes connected between bases of said pair of differential transistors and said current source, respectively; two post-amplifiers each having two amplification transistors which receive their input signals at their emitters, said post-amplifiers being connected to two of said plurality of pre-amplification circuits; and connection wires relatively long when compared with a circuit scale and connected between said two pre-amplification circuits and said post-amplifiers, wherein the collectors of the first, second, third and fourth amplification transistors of one of said two pre-amplification circuits are connected respectively to the collectors of the corresponding transistors of the other pre-amplification circuit and also connected to one of the two amplification transistors of said two post-amplifiers, and the collectors of the first, second, third and fourth amplification transistors connected to the collectors of the differential transistors of the other pre-amplification circuit are connected respectively to the collectors of the corresponding transistors of the other pre-amplification circuit and also connected to the other of the two amplification transistors of said two post-amplifiers.

Claim 18

A magnetic head circuit for magnetic head signals comprising: a plurality of pairs of signal terminals; a plurality of pre-amplification circuits connected respectively to said plurality of pairs of signal terminals, each of said plurality of pre-amplification circuits includes: a pair of differential transistors whose bases are connected to associated one of said pairs of signal terminals and whose emitters are connected directly to each other and which are operated according to a voltage appearing between said pair of signal terminals; first and second amplification transistors whose emitters are connected to one collector of said pair of differential transistors; third and fourth amplification transistors whose emitters are connected to the other collector of another collector of said pair of differential transistors receiving at their bases a first selection signal, said second and fourth amplification transistors receiving at their bases a second selection signal; first diodes connected to the emitters and the bases of said first and said third amplification transistors, respectively; a current source connected to the emitters of said pair of differential transistors, and second diodes connected between bases of said pair of differential transistors and said current source, respectively; two post-amplifiers each having two amplification transistors which receive their input signals at their emitters, said post-amplifiers being connected to two of said plurality of pre-amplification circuits; and connection wires relatively long when compared with a circuit scale and connected between said two pre-amplification circuits and said post-amplifiers, wherein the collectors of the first, second, third and fourth amplification transistors of one of said two pre-amplification circuits are connected respectively to the collectors of the corresponding transistors of the other pre-amplification circuit and also connected to one of the two amplification transistors of said two post-amplifiers, and the collectors of the first, second, third and fourth amplification transistors connected to the collectors of the differential transistors of the other pre-amplification circuit are connected respectively to the collectors of the corresponding transistors of the other pre-amplification circuit and also connected to the other of the two amplification transistors of said two post-amplifiers.

Claim 19

A magnetic head circuit as set forth in claim 16, wherein each of said two post-amplifiers includes two resistors and an output circuit connected to said two amplification transistors, and two signals obtained from said plurality of pairs of signal terminals through said two pre-amplification circuits are output at the same time through said output circuit.

Claim 20

A magnetic head circuit as set forth in claim 16, further comprising means connected in series with said current source for switching the differential operation current to operate said differential transistors in one of a plurality of pairs.

Claim 21

A magnetic head circuit as set forth in claim 18, wherein one of said two signals is a servo disk signal which is obtained from the signal terminals in one of said pairs.

Claim 22

A magnetic head circuit for magnetic head signals comprising: a plurality of pairs of signal terminals; a plurality of pre-amplification circuits connected respectively to said plurality of pairs of signal terminals, each of said plurality of pre-amplification circuits includes: a pair of differential transistors whose bases are connected to an associated one of said pairs of signal terminals and whose emitters are connected directly to each other and which are operated according to a voltage appearing between said pair of signal terminals; an amplification transistor whose emitter is connected to one collector of said pair of transistors and an amplification transistor whose emitter is connected to the other collector; a current source connected to the emitters of said pair of differential transistors for providing a differential operation thereto; and a plurality of diodes connected in parallel between the emitters and bases of said pair of differential transistors; post-amplifiers each having two amplification transistors which receive their input signals at their emitters and which are connected to said plurality of pre-amplification circuits; and connection wires relatively long when compared with a circuit scale and connected between said plurality of pre-amplification circuits and said post-amplifiers.

Claim 23

A magnetic head circuit for magnetic head signals comprising: a plurality of pairs of signal terminals; a plurality of pre-amplification circuits connected respectively to said plurality of pairs of signal terminals, each of said plurality of pre-amplification circuits includes: a pair of differential transistors whose bases are connected to an associated one of said pairs of signal terminals and whose emitters are connected directly to each other and which are operated according to a voltage appearing between said pair of signal terminals; an amplification transistor whose emitter is connected to one collector of said pair of transistors and an amplification transistor whose emitter is connected to the other collector; a current source connected to the emitters of said pair of differential transistors for providing a differential operation thereto; and a plurality of diodes connected in parallel between the emitters and bases of said pair of differential transistors; post-amplifiers each having two amplification transistors which receive their input signals at their emitters and which are connected to said plurality of pre-amplification circuits; and connection wires relatively long when compared with a circuit scale and connected between said plurality of pre-amplification circuits and said post-amplifiers.

Claim 24

A magnetic head circuit as set forth in claim 20, further comprising an offset adjustment circuit having two input and memory circuits connected to the collectors of the amplification transistors connected to the collectors of the differential transistors of one and the other of said plurality of pre-amplification circuits for adjusting offset voltages in said plurality of pre-amplification circuits.

Claim 25

A magnetic head circuit as set forth in claim 21, wherein said memory circuit has therein adjustment data relating to said plurality of pre-amplification circuits.

Claim 26

A magnetic head circuit as set forth in claim 21, wherein said memory circuit has predetermined data relating to inner and outer peripheries of disk, and said offset adjustment circuit receives information on a track position on the disk and applies the received information to predetermined current signals of said post-amplifiers.

Claim 27

A magnetic head circuit as set forth in claim 21, wherein said adjustment circuit includes a pair of differential transistors, a plurality of other pairs of differential transistors whose collectors are connected to bases of said pair of differential transistors and whose emitters are connected in pairs, and a resistor ladder circuit of resistors connected to the emitters of said plurality of pairs of differential transistors, said resistors having different respective impedances.

Claim 28

A magnetic head circuit for a plurality of magnetic heads, comprising: two emitter follower transistors for receiving magnetic head writing data; two differential transistors connected to said two emitter follower transistors for performing differential operation control thereover; and two resistors connected to collectors of said two differential transistors for supplying a base current to said two emitter follower transistors, wherein said emitter follower transistors are connected in series with each other to perform differential switch operation over a magnetic head writing current.

Claim 29

A magnetic head circuit for a plurality of magnetic heads, comprising: two emitter follower transistors for receiving magnetic head writing data; two differential transistors connected to said two emitter follower transistors for performing differential operation control thereover; and two resistors connected to collectors of said two differential transistors for supplying a base current to said two emitter follower transistors, wherein said emitter follower transistors are connected in series with each other to perform differential switch operation over a magnetic head writing current.