US5390136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Artificial neuron and method of using same
Assignee: Motorola Solutions Inc
•
Filing: 1993-06-14
•
Granted: 1995-02-14
•
Expires: 2013-06-14
Abstract
Abstract An artificial neuron, which may be implemented either in hardware or software, has only one significant processing element in the form of a multiplier. Inputs are first fed through gating functions to produce gated inputs. These gated inputs are then multiplied together to produce a product which is multiplied by a weight to produce the neuron output.
Inventors
- 👤 Shay-Ping T. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:14
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/552; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063; G06F2207/00; G06F2207/552; G06F2207/5523
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
224 words
A neuron circuit comprising: first latch means responsive to a plurality of inputs x i for sequentially storing each of said inputs x i and for sequentially providing each of said stored inputs x i as an output thereof, wherein i is a positive integer; counter/latch means responsive to the output of said first latch means and providing said stored inputs as an output thereof; second latch means for providing an output; a multiplier circuit having a first input responsive to the output of said counter/latch means and a second input responsive to the output of said second latch means, and generating a product; a multiplexer for coupling either said product or a weight value W to an input of said second latch means; and wherein said counter/latch means includes means, responsive to a plurality of values g i , there being a value g i corresponding to each value x i , for counting g i multiplication cycles of said multiplier circuit: and wherein said multiplier includes means for multiplying said input x i by said product during each of said multiplication cycles, and for multiplying said product by said weight value during one of said multiplication cycles; whereby said neuron circuit generates an output of the form W x 1 g 1 x 2 g 2. . . x n g n.
Claim 2
Dependent Claim
224 words
A neuron circuit comprising: first latch means responsive to a plurality of inputs x i for sequentially storing each of said inputs x i and for sequentially providing each of said stored inputs x i as an output thereof, wherein i is a positive integer; counter/latch means responsive to the output of said first latch means and providing said stored inputs as an output thereof; second latch means for providing an output; a multiplier circuit having a first input responsive to the output of said counter/latch means and a second input responsive to the output of said second latch means, and generating a product; a multiplexer for coupling either said product or a weight value W to an input of said second latch means; and wherein said counter/latch means includes means, responsive to a plurality of values g i , there being a value g i corresponding to each value x i , for counting g i multiplication cycles of said multiplier circuit: and wherein said multiplier includes means for multiplying said input x i by said product during each of said multiplication cycles, and for multiplying said product by said weight value during one of said multiplication cycles; whereby said neuron circuit generates an output of the form W x 1 g 1 x 2 g 2. . . x n g n.
Claim 3
Dependent Claim
52 words
The neuron circuit recited in claim 1, and further comprising an output latch having a first input responsive to said product and a second input responsive to said weight value W, and generating an output representing the output of said neuron circuit, whereby said weight value W can bypass said multiplier circuit.
Claim 4
Dependent Claim
19 words
The neuron circuit recited in claim 1, wherein said first latch means is responsive to an input clock signal.
Claim 5
Dependent Claim
31 words
The neuron circuit of recited in claim 3, wherein said input clock signal is generated by a clock generator when the value of g i in said counter/latch means is zero.
Claim 6
Dependent Claim
18 words
The neuron circuit recited in claim 1, wherein said counter/latch means is responsive to an internal clock signal.
Claim 7
Dependent Claim
20 words
The neuron circuit recited in claim 1, wherein said second latch means is responsive to an internal clock signal (CLK).
Claim 8
Dependent Claim
19 words
The neuron circuit recited in claim 1, wherein each of said inputs x i comprises a plurality of bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |