US5387879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gain controllable output buffer amplifier circuit having a reduced circuit area
Assignee: Renesas Electronics Corp
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Filing: 1993-08-04
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Granted: 1995-02-07
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Expires: 2013-08-04
Abstract
Abstract A gain-controllable output buffer amplifier circuit includes an operational amplifier having a grounded non-inverting input and an inverting input connected through an input resistor to a signal input node. A tapped feedback resistor having a plurality of intermediate taps is connected between an output and the inverting input of the operational amplifier. Each of the intermediate taps is connected through a transistor switch in common to a non-inverting input of an output buffer amplifier, which has its output connected to a signal output node and an inverting input of the output buffer amplifier itself. The transistor switches are controlled by a switch control circuit in such a manner that only one of transistors switches is selectively turned on.
Inventors
- 👤 Noritoshi Satoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:52
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0088
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
238 words
An output buffer amplifier circuit comprising: an operational amplifier having an inverting input and a non-inverting input, one of which is connected to a signal input node, said inverting input of said operational amplifier being connected through an input resistor to said signal input node, said non-inverting input of said operational amplifier being connected directly to the ground; a feedback resistor having its one end connected to an output of said operational amplifier and its other end connected to said inverting input of said operational amplifier, said feedback resistor having a plurality of intermediate taps; a corresponding number of transistor switches each of which has its one end connected to a corresponding one of said plurality of intermediate taps of said feedback resistor, each of said transistor switches being formed of a CMOS transfer gate composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel to each other, an output buffer amplifier having its input connected in common to the other end of each of said transistor switches, an output of said output buffer amplifier being connected to an output node; and a switch control circuit connected to a control input of said transistor switches so as to turn on only a selected one of said transistor switches, gates of said P-channel MOS transistor and said N-channel MOS transistor being connected to receive a pair of complementary control signals from said switch control circuit.
Claim 2
Dependent Claim
238 words
An output buffer amplifier circuit comprising: an operational amplifier having an inverting input and a non-inverting input, one of which is connected to a signal input node, said inverting input of said operational amplifier being connected through an input resistor to said signal input node, said non-inverting input of said operational amplifier being connected directly to the ground; a feedback resistor having its one end connected to an output of said operational amplifier and its other end connected to said inverting input of said operational amplifier, said feedback resistor having a plurality of intermediate taps; a corresponding number of transistor switches each of which has its one end connected to a corresponding one of said plurality of intermediate taps of said feedback resistor, each of said transistor switches being formed of a CMOS transfer gate composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel to each other, an output buffer amplifier having its input connected in common to the other end of each of said transistor switches, an output of said output buffer amplifier being connected to an output node; and a switch control circuit connected to a control input of said transistor switches so as to turn on only a selected one of said transistor switches, gates of said P-channel MOS transistor and said N-channel MOS transistor being connected to receive a pair of complementary control signals from said switch control circuit.
Claim 3
Dependent Claim
184 words
An output buffer amplifier circuit comprising: an operational amplifier having an inverting input and a non-inverting input, one of which is connected to a signal input node, said non-inverting input of said operational amplifier being connected directly to said signal input node, and said inverting input of said operational amplifier being connected through a ground resistor to the ground; a feedback resistor having its one end connected to an output of said operational amplifier and its other end connected to said inverting input of said operational amplifier, said feedback resistor having a plurality of intermediate taps; a corresponding number of transistor switches each of which has its one end connected to a corresponding one of said plurality of intermediate taps of said feedback resistor; an output buffer amplifier having its input connected in common to the other end of each of said transistor switches, an output of said output buffer amplifier being connected to an output node; and a switch control circuit connected to a control input of said transistor switches so as to turn on only a selected one of said transistor switches.
Claim 4
Dependent Claim
184 words
An output buffer amplifier circuit comprising: an operational amplifier having an inverting input and a non-inverting input, one of which is connected to a signal input node, said non-inverting input of said operational amplifier being connected directly to said signal input node, and said inverting input of said operational amplifier being connected through a ground resistor to the ground; a feedback resistor having its one end connected to an output of said operational amplifier and its other end connected to said inverting input of said operational amplifier, said feedback resistor having a plurality of intermediate taps; a corresponding number of transistor switches each of which has its one end connected to a corresponding one of said plurality of intermediate taps of said feedback resistor; an output buffer amplifier having its input connected in common to the other end of each of said transistor switches, an output of said output buffer amplifier being connected to an output node; and a switch control circuit connected to a control input of said transistor switches so as to turn on only a selected one of said transistor switches.
Claim 5
Dependent Claim
77 words
A output buffer amplifier circuit claimed in claim 2 wherein ground resistor has a plurality of intermediate taps, which are connected through corresponding transistor switches in common to said input of said output buffer amplifier, and said transistor switches connected to said taps of said feedback resistor and said transistor switches connected to said taps of said ground resistor are controlled by said switch control circuit so that only one of these transistor switches are turned on.
Claim 6
Dependent Claim
65 words
A output buffer amplifier circuit claimed in claim 3 wherein each of said transistor switches is formed of a CMOS transfer gate composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel to each other, gates of said P-channel MOS transistor and said N-channel MOS transistor being connected to receive a pair of complementary control signals from said switch control circuit.
Claim 7
Dependent Claim
189 words
An output buffer amplifier circuit comprising: an amplification circuit connected to a signal input node and having an operational amplifier and a feedback resistor having its one end connected to an output of said operational amplifier and its other end connected to an inverting input of said operational amplifier, said operational amplifier having a non-inverting input connected directly to said signal input node, and said inverting input of said operational amplifier being connected through a ground resistor to the ground, so that said amplification circuit has a constant amplification factor, said feedback resistor having a plurality of intermediate taps; a corresponding number of transistor switches each of which has its one end connected to a corresponding one of said plurality of intermediate taps of said feedback resistor; an output buffer amplifier having a high impedance input connected in common to the other end of each of said transistor switches, an output of said output buffer amplifier being connected to an output node; and a switch control circuit connected to a control input of said transistor switches so as to turn on only a selected one of said transistor switched.
Claim 8
Dependent Claim
189 words
An output buffer amplifier circuit comprising: an amplification circuit connected to a signal input node and having an operational amplifier and a feedback resistor having its one end connected to an output of said operational amplifier and its other end connected to an inverting input of said operational amplifier, said operational amplifier having a non-inverting input connected directly to said signal input node, and said inverting input of said operational amplifier being connected through a ground resistor to the ground, so that said amplification circuit has a constant amplification factor, said feedback resistor having a plurality of intermediate taps; a corresponding number of transistor switches each of which has its one end connected to a corresponding one of said plurality of intermediate taps of said feedback resistor; an output buffer amplifier having a high impedance input connected in common to the other end of each of said transistor switches, an output of said output buffer amplifier being connected to an output node; and a switch control circuit connected to a control input of said transistor switches so as to turn on only a selected one of said transistor switched.
Claim 9
Dependent Claim
77 words
A output buffer amplifier circuit claimed in claim 5 wherein ground resistor has a plurality of intermediate taps, which are connected through corresponding transistor switches in common to said input of said output buffer amplifier, and said transistor switches connected to said taps of said feedback resistor and said transistor switches connected to said taps of said ground resistor are controlled by said switch control circuit so that only one of these transistor switches are turned on.
References Cited (Backward Citations)
US4599574A
Cited
JPH03232310A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |