Method of making dynamic random access memory

Claim 1

A method of making a DRAM comprising the steps of: (a) forming first and second field insulation films with a constant interval on a top surface of a semiconductor substrate, to define an active region; (b) forming word lines uniformly spaced from each other respectively on said first and second field insulation films and said active region, wherein each word line includes side wall insulation films at side walls thereof; (c) forming a third insulation film for a capacitor contact by exposing a third insulation pattern on said top surface and then removing portions formed between the word lines of the active region and the word lines of said first and second field insulation films, of said third insulation film, to form capacitor contact holes; (d) implanting an impurity on the semiconductor substrate through the capacitor contact holes, to form impurity regions in the surface of the semiconductor substrate; (e) forming a first conductor of a predetermined thickness for a plug by exposing a first conductor pattern on said top surface and then etching-back the first conductor for said plug until said third insulation film for the capacitor contact is exposed, thereby forming plug conductors on the surface of said third insulation film for the capacitor contact and in the capacitor contact holes and planarizing the entirety of said top surface; (f) forming a fourth insulation film for a buffer layer by exposing a fourth insulation pattern on said top surface and removing a portion formed between two word lines of the active region, of said fourth insulation film for the buffer layer, the remaining third insulation film for the capacitor contact and the plug conductors, to form a bit line contact; (g) forming a second conductor for a bit line contact hole and a fifth insulation film for bit line definition, in this order, by exposing a second conductor pattern and a fifth insulation pattern on said top surface so that the bit line contact hole is filled by said second conductor and said fifth insulation film, wherein the second conductor for the bit line contact hole and the fifth insulation film for bit line definition have planarizing surfaces, respectively; (h) covering a first etch mask having a width wider than a width of the bit line contact on the upper portion of the bit line contact hole, of the surface of the fifth insulation film for the bit line definition, and then etching the fifth insulation film for bit line definition, the second conductor for the bit line and the fourth insulation film for the buffer layer to form a bit line; (i) removing said first etch mask and then forming a sixth insulation film for bit line insulation, and forming a third conductor for a plate node having a planarizing surface and a seventh insulation film for capacitor definition, in this order, by exposing a sixth insulation pattern, a third conductor pattern and a seventh insulation pattern on said top surface; (j) forming a second etch mask having a width that is the same as a width of the first etch mask at an upper part of the bit line, of the surface of the seventh insulation film for capacitor definition, and then etching the third conductor for the plate node and the seventh insulation film for capacitor definition; (k) forming a first dielectric film for capacitor dielectric and a fourth conductor for the storage node, in this order, by exposing a first dielectric pattern and a fourth conductor pattern on said top surface and then etching said first dielectric film and said fourth conductor together with the sixth insulation film for bit line insulation so that portions formed at the side walls of the remaining third conductor for the plate node and the seventh insulation film for capacitor definition merely remain; (l) forming a fifth conductor for the storage node by exposing a fifth conductor pattern on said top surface and then patterning said fifth conductor to merely remove a portion formed at the surface of the remaining seventh insulation film for capacitor definition and thus complete the storage node; (m) forming a second dielectric film for a capacitor dielectric by exposing a second dielectric film pattern on said top surface and then removing the remaining seventh insulation film for capacitor definition and the second dielectric film formed on the seventh insulation film to complete a capacitor dielectric; and (n) forming a sixth conductor by exposing a sixth conductor pattern on said top surface to complete the plate node.

Claim 2

A method of making a DRAM comprising the steps of: (a) forming first and second field insulation films with a constant interval on a top surface of a semiconductor substrate, to define an active region; (b) forming word lines uniformly spaced from each other respectively on said first and second field insulation films and said active region, wherein each word line includes side wall insulation films at side walls thereof; (c) forming a third insulation film for a capacitor contact by exposing a third insulation pattern on said top surface and then removing portions formed between the word lines of the active region and the word lines of said first and second field insulation films, of said third insulation film, to form capacitor contact holes; (d) implanting an impurity on the semiconductor substrate through the capacitor contact holes, to form impurity regions in the surface of the semiconductor substrate; (e) forming a first conductor of a predetermined thickness for a plug by exposing a first conductor pattern on said top surface and then etching-back the first conductor for said plug until said third insulation film for the capacitor contact is exposed, thereby forming plug conductors on the surface of said third insulation film for the capacitor contact and in the capacitor contact holes and planarizing the entirety of said top surface; (f) forming a fourth insulation film for a buffer layer by exposing a fourth insulation pattern on said top surface and removing a portion formed between two word lines of the active region, of said fourth insulation film for the buffer layer, the remaining third insulation film for the capacitor contact and the plug conductors, to form a bit line contact; (g) forming a second conductor for a bit line contact hole and a fifth insulation film for bit line definition, in this order, by exposing a second conductor pattern and a fifth insulation pattern on said top surface so that the bit line contact hole is filled by said second conductor and said fifth insulation film, wherein the second conductor for the bit line contact hole and the fifth insulation film for bit line definition have planarizing surfaces, respectively; (h) covering a first etch mask having a width wider than a width of the bit line contact on the upper portion of the bit line contact hole, of the surface of the fifth insulation film for the bit line definition, and then etching the fifth insulation film for bit line definition, the second conductor for the bit line and the fourth insulation film for the buffer layer to form a bit line; (i) removing said first etch mask and then forming a sixth insulation film for bit line insulation, and forming a third conductor for a plate node having a planarizing surface and a seventh insulation film for capacitor definition, in this order, by exposing a sixth insulation pattern, a third conductor pattern and a seventh insulation pattern on said top surface; (j) forming a second etch mask having a width that is the same as a width of the first etch mask at an upper part of the bit line, of the surface of the seventh insulation film for capacitor definition, and then etching the third conductor for the plate node and the seventh insulation film for capacitor definition; (k) forming a first dielectric film for capacitor dielectric and a fourth conductor for the storage node, in this order, by exposing a first dielectric pattern and a fourth conductor pattern on said top surface and then etching said first dielectric film and said fourth conductor together with the sixth insulation film for bit line insulation so that portions formed at the side walls of the remaining third conductor for the plate node and the seventh insulation film for capacitor definition merely remain; (l) forming a fifth conductor for the storage node by exposing a fifth conductor pattern on said top surface and then patterning said fifth conductor to merely remove a portion formed at the surface of the remaining seventh insulation film for capacitor definition and thus complete the storage node; (m) forming a second dielectric film for a capacitor dielectric by exposing a second dielectric film pattern on said top surface and then removing the remaining seventh insulation film for capacitor definition and the second dielectric film formed on the seventh insulation film to complete a capacitor dielectric; and (n) forming a sixth conductor by exposing a sixth conductor pattern on said top surface to complete the plate node.