US5387532A
Expired / Lapsed
US
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Semiconductor memory having capacitor electrode formed above bit line
Assignee: Toshiba Corp
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Filing: 1993-08-10
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Granted: 1995-02-07
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Expires: 2013-08-10
Abstract
Abstract A semiconductor memory has many memory cells of which each has a transistor and a capacitor. In each memory cell, one of source and drain regions of the transistor is connected to a bit line formed above the transistor. The capacitor includes a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line. To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of the first capacitor electrode, and a second capacitor electrode is formed on the insulation film.
Inventors
- 👤 Takeshi Hamamoto
- 👤 Fumio Horiguchi
- 👤 Katsuhiko Hieda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:14
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; Y; Y10; Y10S; Y10S257/00; Y10S257/905; Y10S257/908
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
232 words
A method of manufacturing a semiconductor memory having memory cells, each composed of a transistor and a capacitor formed on a semiconductor substrate, the method comprising the steps of: forming a gate electrode on a gate insulation film in each memory cell region where said memory cells are to be formed on the semiconductor substrate; forming source and drain regions in the memory cell region by doping the semiconductor substrate with impurities, using the gate electrode as a mask; forming a bit line for the memory cell region and connecting the bit line to one of the source and drain regions; forming pad electrodes for the memory cell region, for connecting the bit line with one of the source and drain regions of the transistor and for connecting the electrode with the other of the source and drain regions of the transistor, wherein said pad electrode for connecting the bit line with one of the source and drain regions of the transistor is formed so as to be separated from the memory cell region; forming a first capacitor electrode for the memory cell region above the bit line and connecting the first capacitor electrode to the other of the source and drain regions which is not connected to the bit line; and forming a second capacitor electrode for the memory cell region on an insulation film formed on the first capacitor electrode.
Claim 2
Independent Claim
232 words
A method of manufacturing a semiconductor memory having memory cells, each composed of a transistor and a capacitor formed on a semiconductor substrate, the method comprising the steps of: forming a gate electrode on a gate insulation film in each memory cell region where said memory cells are to be formed on the semiconductor substrate; forming source and drain regions in the memory cell region by doping the semiconductor substrate with impurities, using the gate electrode as a mask; forming a bit line for the memory cell region and connecting the bit line to one of the source and drain regions; forming pad electrodes for the memory cell region, for connecting the bit line with one of the source and drain regions of the transistor and for connecting the electrode with the other of the source and drain regions of the transistor, wherein said pad electrode for connecting the bit line with one of the source and drain regions of the transistor is formed so as to be separated from the memory cell region; forming a first capacitor electrode for the memory cell region above the bit line and connecting the first capacitor electrode to the other of the source and drain regions which is not connected to the bit line; and forming a second capacitor electrode for the memory cell region on an insulation film formed on the first capacitor electrode.
Claim 3
Dependent Claim
44 words
The method as claimed in claim 1, wherein the bit line is disposed on an element separating region between memory cell regions, and the bit line extends orthogonally to a word line, which word line is composed of a gate electrode of the transistor.
Claim 4
Dependent Claim
21 words
The method as claimed in claim 1, wherein said transistor is a MOS transistor, and said capacitor is a MOS capacitor.
Claim 5
Dependent Claim
22 words
The method as claimed in claim 3, wherein one of source and drain regions of the MOS transistor contacts the bit line.
Claim 6
Dependent Claim
35 words
The method as claimed in claim 3, wherein the bit line is disposed on a memory cell region and orthogonally to a word line which is composed of a gate electrode of the MOS transistor.
Claim 7
Dependent Claim
35 words
The method as claimed in claim 1, wherein opposite surfaces of said first and second capacitor electrodes are formed unevenly in order to increase the interfacial area therebetween with the intervention of said insulation film.
Claim 8
Dependent Claim
18 words
The method as claimed in claim 6, wherein grooves are formed in said first and second capacitor electrodes.
Claim 9
Dependent Claim
30 words
The method as claimed in claim 1, further comprising the step of separating each adjacent memory cell by forming a groove therebetween and filling said groove with an insulating material.
Claim 10
Dependent Claim
14 words
The method as claimed in claim 8, wherein said insulating material is silicon oxide.
Claim 11
Dependent Claim
16 words
The method as claimed in claim 8, wherein said insulating material is a non-doped polycrystalline silicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |