US5384529A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current limiting circuit and method of manufacturing same
Assignee: NEC Electronics Corp
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Filing: 1994-01-28
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Granted: 1995-01-24
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Expires: 2014-01-28
Abstract
Abstract A current limiting circuit which includes a vertical MOS transistor as an output transistor has a clamping voltage that can be established with high accuracy, and once established, is less dependent on temperature. The gate of an output N-channel VDMOS transistor is connected to a constant-voltage circuit composed of an N-channel VDMOS transistor having the same characteristics as those of the output N-channel VDMOS transistor and two series-connected resistors which supply a divided voltage to the gate of the N-channel VDMOS transistor. The clamping voltage between the gate and source of the output N-channel VDMOS transistor can be adjusted based on the voltage divided by the resistors of the constant-voltage circuit. The temperature characteristics of the output N-channel VDMOS transistor and the constant-voltage circuit are held in phase with each other to reduce variations in the clamping voltage caused by temperature variations.
Inventors
- 👤 Manabu Nakago
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:48
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
157 words
A current limiting circuit comprising: an output first N-channel vertical MOS transistor having a gate to which is supplied an input signal, a drain to which is supplied a power supply potential through a load, and a source connected to ground; an N-channel MOS transistor having a gate connected to the drain of said first N-channel vertical MOS transistor and a source connected to ground; first and second resistors connected in series between the gate of said first N-channel vertical MOS transistor and a drain of said N-channel MOS transistor; and a second N-channel vertical MOS transistor having the same characteristics as those of said first N-channel vertical MOS transistor, said second N-channel vertical MOS transistor having a drain connected to the gate of said first N-channel vertical MOS transistor, a source connected to the drain of said N-channel MOS transistor, and a gate to which is supplied a voltage divided by said first and second resistors.
Claim 2
Dependent Claim
157 words
A current limiting circuit comprising: an output first N-channel vertical MOS transistor having a gate to which is supplied an input signal, a drain to which is supplied a power supply potential through a load, and a source connected to ground; an N-channel MOS transistor having a gate connected to the drain of said first N-channel vertical MOS transistor and a source connected to ground; first and second resistors connected in series between the gate of said first N-channel vertical MOS transistor and a drain of said N-channel MOS transistor; and a second N-channel vertical MOS transistor having the same characteristics as those of said first N-channel vertical MOS transistor, said second N-channel vertical MOS transistor having a drain connected to the gate of said first N-channel vertical MOS transistor, a source connected to the drain of said N-channel MOS transistor, and a gate to which is supplied a voltage divided by said first and second resistors.
Claim 3
Dependent Claim
156 words
A current limiting circuit comprising: an output first N-channel vertical MOS transistor having a gate to which is supplied an input signal, a drain to which is supplied a power supply potential, and a source connected to a load; an N-channel MOS transistor having a gate connected to the drain of said first N-channel vertical MOS transistor and a drain connected to the gate of said first N-channel vertical MOS transistor; first and second resistors connected in series between a source of said N-channel MOS transistor and said load; and a second N-channel vertical MOS transistor having the same characteristics as those of said first N-channel vertical MOS transistor, said second N-channel vertical MOS transistor having a drain connected to the source of said N-channel MOS transistor, a source connected to the source of said first N-channel vertical MOS transistor, and a gate to which is supplied a voltage divided by said first and second resistors.
Claim 4
Dependent Claim
156 words
A current limiting circuit comprising: an output first N-channel vertical MOS transistor having a gate to which is supplied an input signal, a drain to which is supplied a power supply potential, and a source connected to a load; an N-channel MOS transistor having a gate connected to the drain of said first N-channel vertical MOS transistor and a drain connected to the gate of said first N-channel vertical MOS transistor; first and second resistors connected in series between a source of said N-channel MOS transistor and said load; and a second N-channel vertical MOS transistor having the same characteristics as those of said first N-channel vertical MOS transistor, said second N-channel vertical MOS transistor having a drain connected to the source of said N-channel MOS transistor, a source connected to the source of said first N-channel vertical MOS transistor, and a gate to which is supplied a voltage divided by said first and second resistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |