Protective system for insertion/extraction of PC boards in a powered-up environment

Claim 2

Apparatus for minimizing rapid current variations in a power supply supplying the circuitry elements of a printed circuit board comprising: (a) a backplane for connection to said printed circuit board, said backplane including: (a1) a plurality of male connecting pins of specified different lengths which initiate a timed sequence period of connection to the female sockets of said printed circuit board; (a2) an N-Volt power supply supplying N volt potential to particular ones of said male connecting pins; (b) said printed circuit board including: (b1) a plurality of female connection sockets which align correspondingly to said male connection pins; (b2) a current variation minimization circuit which acts to slow down changes in current drawn by said printed circuit board from said N-volt power supply during the said sequence period of connection, said current variation minimization circuit including: (b2a) a plurality of Field Effect Transistors (FET) forming a FET Group, each FET having a Source Terminal (S), a Gate Terminal (G), and a Drain Terminal, (D); (b2b) resistor-capacitor circuit elements connecting said N-volt power supply to each Gate G of said FET Group; (b2c) a card ground connecting each Drain D to a ground terminal on said printed circuit board; (b2d) said Source S of each FET group connected to a precharge ground socket terminal on said printed circuit board.

Claim 3

The apparatus of claim 1 wherein said plurality of male connection pins includes: (a) a first precharge voltage pin of length "L" providing an N-volt potential from N-volt power supply; (b) a second precharge ground pin of length "L" providing a preliminary ground connection to said backplane; (c) a third voltage (V cc ) pin of length range from 2/3 L to "3/4 L" for providing N-volts to power said circuitry elements on said printed circuit board when connected to said printed circuit board; (d) a fourth FET ground pin of length range from 2/3 L to "3/4 L" for backplane grounding the Source (S) terminals of said Field Effect Transistor (FET) Group when connected to said printed circuit board; (e) a fifth ramp circuit pin of length range of 1/3 L to 1/2 L for providing said N-volt potential to said Gate terminals of said FET Group when connected to said printed circuit board; (f) a sixth direct ground pin of length range 1/10 L to 1/4 L for applying a backplane ground connection to said drains D of said FET Group when connected to said printed circuit board.

Claim 4

Apparatus for minimizing rapid current variations in an N-volt power supply supplying the circuitry elements of a printed circuit board comprising: (a) a backplane to be disconnected from its connection to said printed circuit board, said backplane including: (a1) a plurality of male connection pins of specified different lengths which initiate a time sequence period of disconnection to the female sockets of said printed circuit board; (a2) an N-Volt power supply supplying N volt potential to particular ones of said male connection pins; (b) said printed circuit board including: (b1) a plurality of female sockets which align correspondingly to said male connection pins; (b2) a current variation minimization circuit which acts to slow down changes in current drawn by said printed circuit board from said N-volt power supply during the said sequence period of disconnection, wherein said current variation minimization circuit includes: (b2a) a plurality of Field Effect Transistors (FET) forming a FET Group, each FET having a Source Terminal (S), a Gate Terminal (G), and a Drain Terminal, (D); (b2b) resistor-capacitor circuit elements connecting said N-volt power supply to each Gate G of said FET Group; (b2c) a card ground connecting each Drain D to a ground terminal on said printed circuit board; (b2d) said Source S of each FET group connected to a precharge ground socket terminal on said printed circuit board.

Claim 5

Apparatus for minimizing rapid current variations in an N-volt power supply supplying the circuitry elements of a printed circuit board comprising: (a) a backplane to be disconnected from its connection to said printed circuit board, said backplane including: (a1) a plurality of male connection pins of specified different lengths which initiate a time sequence period of disconnection to the female sockets of said printed circuit board; (a2) an N-Volt power supply supplying N volt potential to particular ones of said male connection pins; (b) said printed circuit board including: (b1) a plurality of female sockets which align correspondingly to said male connection pins; (b2) a current variation minimization circuit which acts to slow down changes in current drawn by said printed circuit board from said N-volt power supply during the said sequence period of disconnection, wherein said current variation minimization circuit includes: (b2a) a plurality of Field Effect Transistors (FET) forming a FET Group, each FET having a Source Terminal (S), a Gate Terminal (G), and a Drain Terminal, (D); (b2b) resistor-capacitor circuit elements connecting said N-volt power supply to each Gate G of said FET Group; (b2c) a card ground connecting each Drain D to a ground terminal on said printed circuit board; (b2d) said Source S of each FET group connected to a precharge ground socket terminal on said printed circuit board.

Claim 6

The apparatus of claim 3 wherein said plurality of male connection pins, when connected to said printed circuit board, includes: (a) a first precharge voltage pin of length "L" providing an N-volt potential from said N-volt power supply; (b) a second precharge ground pin of length "L" providing a preliminary ground connection to said backplane; (c) a third voltage (V cc ) pin of length range from 2/3 L to 3/4 L for providing N-volts to power said circuitry elements on said printed circuit board when connected to said printed circuit board; (d) a fourth FET ground pin of length range from 2/3 L to 3/4 L for backplane grounding the Source (S) terminals of said Field Effect Transistor (FET) Group when connected to said printed circuit board; (e) a fifth ramp circuit pin of length range from 1/3 L to 1/2 L for providing said N-volt potential to said Gate terminals of said FET Group when connected to said printed circuit board; (f) a sixth direct ground pin of length range 1/10 L to 1/4 L for applying a backplane ground connection to the drains D of said FET Group when connected to said printed circuit board.

Claim 7

In a system for connecting a digital module holding electronic resource elements and a temporary load-control means using a group of field effect transistors (FETs), to an empowered backplane holding an N-volt power source and a set of connecting pins of predetermined different lengths which will enable a time-sequenced set of connection between said backplane and digital module, a method for minimizing variations in current-load on said power supply comprising the steps of: (a) firstly, connecting a set of two pins of length L to charge the Source-Drain capacitance of a group of field effect transistors (FETs) to initially prevent conduction through said FETs; (b) secondly, connecting a set of 2 pins, each of approximate length, 2/3 L, to empower the circuit resource elements on said digital module and to ground the Source terminals of said group of FETs; (c) thirdly, connecting a pin of approximate length 1/2 L to provide N volts through a delay circuit to charge the gates G of said group of FETs and permit current conduction therethrough; (d) fourthly, connecting a ground pin of approximate length 1/4 L, to the Drain (D) terminals of said group of FETs in order to carry the current load and to shut off conduction through said group of FETs.

Claim 8

In a system for connecting a digital module holding electronic resource elements and a temporary load-control means using a group of field effect transistors (FETs), to an empowered backplane holding an N-volt power source and a set of connecting pins of predetermined different lengths which will enable a time-sequenced set of connection between said backplane and digital module, a method for minimizing variations in current-load on said power supply comprising the steps of: (a) firstly, connecting a set of two pins of length L to charge the Source-Drain capacitance of a group of field effect transistors (FETs) to initially prevent conduction through said FETs; (b) secondly, connecting a set of 2 pins, each of approximate length, 2/3 L, to empower the circuit resource elements on said digital module and to ground the Source terminals of said group of FETs; (c) thirdly, connecting a pin of approximate length 1/2 L to provide N volts through a delay circuit to charge the gates G of said group of FETs and permit current conduction therethrough; (d) fourthly, connecting a ground pin of approximate length 1/4 L, to the Drain (D) terminals of said group of FETs in order to carry the current load and to shut off conduction through said group of FETs.

Claim 9

The method of claim 5 which includes the step of: (e) fifthly, connecting signal pin connections to said electronic resource elements after the N-volt power source has empowered said digital module.