Computer system having planar board with single interrupt controller and processor card with plural processors and interrupt director

Claim 1

A personal computer comprising: a planar board; a single interrupt controller means mounted on said planar board, said interrupt controller means having a plurality of input lines for exclusively receiving all interrupts from a plurality of interrupting devices, an output line, means for transmitting a first interrupt request on said output line in response to receiving a first interrupt on one of said input lines, and a first interrupt vector register for storing an interrupt vector identifying said first interrupt; a multiprocessor upgrade card mounted on said planar board and comprising a plurality of processors and an interrupt director for upgrading said personal computer to operate as a multiprocessor system; said plurality of processors being mounted on said multiprocessor upgrade card, each of said processors having an interrupt request input pin for selectively receiving a second interrupt request; and said interrupt director being mounted on said multiprocessor upgrade card, said interrupt director comprising an input line connected to said output line from said interrupt controller means for receiving said first interrupt request, a plurality of director output lines corresponding in number to the number of said processors and being respectively connected to different interrupt request input pins of said processors, lookup means for storing a plurality of processor identifiers that indicate which processor is assigned to handler each interrupt, a second interrupt vector register, interrupt vector transfer means, and interrupt routing means; said interrupt vector transfer means being operative, in response to said director receiving said first interrupt request, to generate a first interrupt acknowledge cycle during which said interrupt vector is transmitted from said first interrupt vector register to said second interrupt vector register; said interrupt routing means being operative, in response, to receiving said first interrupt request from said interrupt controller means, to first look up in said lookup means the identifier of which processor is assigned to handle said first interrupt and to then generate and transmit said second interrupt request, on only one of said director output lines, to the processor assigned to handle said first interrupt; and said processor assigned to handle said first interrupt being operative, in response to receiving said second interrupt request, to generate a second interrupt acknowledge cycle during which said interrupt vector in said second interrupt vector register is read by such processor to handle said first interrupt.