Interface: interrupt masking with logical sum and product options

Claim 2

Interrupt circuitry for a processor, comprising: (a) a plurality of interrupt input; (b) an interrupt output; (c) combinatorial logic with a plurality of combinatorial logic inputs connected to said plurality of interrupt inputs and with a combinatorial logic output connected to said interrupt output wherein an interrupt output signal at said interrupt output is a function of interrupt signals at said plurality of interrupt inputs; and (d) an interrupt mode select connected to said combinatorial logic wherein an interrupt mode select signal from said interrupt mode select controls said function.

Claim 3

The circuitry of claim 1, wherein: (a) said interrupt mode select signal from said interrupt mode select selects said function to be either AND or OR.

Claim 4

The circuitry of claim 1, further comprising: (a) a mask register having a plurality of mask register inputs and a plurality of mask register outputs, said plurality of mask register inputs connected to said plurality of interrupt inputs and said plurality of mask register outputs connected to said plurality of combinatorial logic inputs wherein a mask register bit pattern in said mask register conditions a corresponding subset (possibly empty) of said interrupt signals at said plurality of interrupt inputs to make said function and said interrupt output signal at said interrupt output not depend upon said corresponding subset.

Claim 5

The circuitry of claim 3, wherein: (a) said interrupt mode select signal at said interrupt mode select selects said function to be either AND or OR; (b) when said function is AND said combinatorial logic ANDs said interrupt signals at said plurality of interrupt inputs, and when said function is OR said combinatorial logic ANDs complements of said interrupt signals at said plurality of interrupt inputs; (c) said mask register bit pattern conditions said corresponding subset of interrupt signals by forcing interrupt signals at said plurality of interrupt inputs and a plurality of complements of said interrupt signals at said plurality of interrupt inputs to a logical 1.

Claim 6

An interface between two processors, comprising: (a) N input buffer registers; (b) N output buffer registers; (c) an N-bit input buffer flag register, wherein a write to one of said input buffer registers sets a corresponding flag bit in said input buffer flag register, and a read of one of said input buffer registers clears a corresponding flag bit in said input buffer flag register; (d) an N-bit output buffer flag register, wherein a write to one of said output buffer registers sets a corresponding flag bit in said output buffer flag register, and a read of one of said output buffer registers clears a corresponding flag bit in said output buffer flag register; (e) an N-bit first input buffer mask register (first IBMR), wherein a bit equal to logical 1 in said first IBMR masks a corresponding bit in said input buffer flag register; (f) an N-bit second input buffer mask register (second IBMR), wherein a bit equal to logical 1 in said second IBMR masks a corresponding bit in said input buffer flag register; (g) an N-bit first output buffer mask register (first OBMR), wherein a bit equal to logical 1 in said first OBMR masks a corresponding bit in said output buffer flag register; (h) an N-bit second output buffer mask register (second OBMR), wherein a bit equal to logical 1 in said second OBMR masks a corresponding bit in said output buffer flag register; (i) first and second input control bits; (j) first and second output control bits; (k) combinatorial logic coupled to both of said flag registers, all of said mask registers, said control bits, and first and second interrupt output nodes, wherein (i) when said first input control bit equals a logical 1 and all of said input buffer registers corresponding to logical 0 in said first IBMR are written to, said logic outputs an interrupt signal at said first interrupt node, but when said first input control bit equals a logical 0 and one of said input buffer registers corresponding to logical 0 in said first IBMR is written to, said logic outputs an interrupt signal at said first interrupt node; (ii) when said second input control bit equals a logical 1 and all of said input buffer registers corresponding to logical 0 in said first IBMR are read, said logic outputs an interrupt signal at said second interrupt node, but when said second input control bit equals a logical 0 and one of said input buffer registers corresponding to logical 0 in said first IBMR is read, said logic outputs an interrupt signal at said second interrupt node; (iii) when said first output control bit equals a logical 1 and all of said output buffer registers corresponding to logical 0 in said first OBMR are read, said logic outputs an interrupt signal at said first interrupt node, but when said first output control bit equals a logical 0 and one of said output buffer registers corresponding to logical 0 in said first OBMR is read, said logic outputs an interrupt signal at said first interrupt node; and (iv) when said second output control bit equals a logical 1 and all of said output buffer registers corresponding to logical 0 in said second OBMR are written to, said logic outputs an interrupt signal at said second interrupt node, but when said second output control bit equals a logical 0 and one of said output buffer registers corresponding to logical 0 in said second OBMR is written to, said logic outputs an interrupt signal at said second interrupt node.

Claim 7

An interface between two processors, comprising: (a) N input buffer registers; (b) N output buffer registers; (c) an N-bit input buffer flag register, wherein a write to one of said input buffer registers sets a corresponding flag bit in said input buffer flag register, and a read of one of said input buffer registers clears a corresponding flag bit in said input buffer flag register; (d) an N-bit output buffer flag register, wherein a write to one of said output buffer registers sets a corresponding flag bit in said output buffer flag register, and a read of one of said output buffer registers clears a corresponding flag bit in said output buffer flag register; (e) an N-bit first input buffer mask register (first IBMR), wherein a bit equal to logical 1 in said first IBMR masks a corresponding bit in said input buffer flag register; (f) an N-bit second input buffer mask register (second IBMR), wherein a bit equal to logical 1 in said second IBMR masks a corresponding bit in said input buffer flag register; (g) an N-bit first output buffer mask register (first OBMR), wherein a bit equal to logical 1 in said first OBMR masks a corresponding bit in said output buffer flag register; (h) an N-bit second output buffer mask register (second OBMR), wherein a bit equal to logical 1 in said second OBMR masks a corresponding bit in said output buffer flag register; (i) first and second input control bits; (j) first and second output control bits; (k) combinatorial logic coupled to both of said flag registers, all of said mask registers, said control bits, and first and second interrupt output nodes, wherein (i) when said first input control bit equals a logical 1 and all of said input buffer registers corresponding to logical 0 in said first IBMR are written to, said logic outputs an interrupt signal at said first interrupt node, but when said first input control bit equals a logical 0 and one of said input buffer registers corresponding to logical 0 in said first IBMR is written to, said logic outputs an interrupt signal at said first interrupt node; (ii) when said second input control bit equals a logical 1 and all of said input buffer registers corresponding to logical 0 in said first IBMR are read, said logic outputs an interrupt signal at said second interrupt node, but when said second input control bit equals a logical 0 and one of said input buffer registers corresponding to logical 0 in said first IBMR is read, said logic outputs an interrupt signal at said second interrupt node; (iii) when said first output control bit equals a logical 1 and all of said output buffer registers corresponding to logical 0 in said first OBMR are read, said logic outputs an interrupt signal at said first interrupt node, but when said first output control bit equals a logical 0 and one of said output buffer registers corresponding to logical 0 in said first OBMR is read, said logic outputs an interrupt signal at said first interrupt node; and (iv) when said second output control bit equals a logical 1 and all of said output buffer registers corresponding to logical 0 in said second OBMR are written to, said logic outputs an interrupt signal at said second interrupt node, but when said second output control bit equals a logical 0 and one of said output buffer registers corresponding to logical 0 in said second OBMR is written to, said logic outputs an interrupt signal at said second interrupt node.

Claim 8

The interface of claim 5, further comprising: (a) first and second status registers; said first status register including said first input control bit, said first output control bit, and a first interrupt control bit and a first interrupt mask bit; and said second status register including said second input control bit, said second output control bit, and a second interrupt control bit and a second interrupt mask bit.

Claim 9

The circuitry of claim 1, wherein said interrupt signals at said plurality of interrupt inputs correspond to an occurrence of an event.

Claim 10

The circuitry of claim 7, wherein said event is selected from the group consisting reading from a buffer register, writing to a buffer register, or any combination thereof.

Claim 11

The circuitry of claim 1, wherein said interrupt signals at said plurality of interrupt inputs correspond to at least one bit in said interrupt signals at said plurality of interrupt inputs.

Claim 12

The circuitry of claim 1, wherein said plurality of interrupt inputs and said interrupt output are selected from the group consisting of flags in a register, pins, and nodes.

Claim 13

The circuitry of claim 1, further comprising: (a) a mask register having a plurality of mask register inputs and a plurality of mask register outputs, said plurality of mask register inputs connected to said plurality of interrupt inputs and said plurality of mask register outputs connected to said plurality of combinatorial logic inputs wherein a mask register bit pattern in said mask register enables/disables a corresponding subset of said interrupt signals at said plurality of interrupt inputs to make said function and said interrupt output signal at said interrupt output depend/not depend upon said corresponding subset.

Claim 14

The circuitry of claim 11, wherein: (a) said interrupt mode signal at said interrupt mode select selects said function to be either AND or OR; (b) when said function is AND said combinatorial logic ANDs said interrupt signals at said plurality of interrupt inputs, and when said function is OR said combinatorial logic ANDs a plurality of complements of said interrupt signals at said plurality of interrupt inputs; (c) said mask register bit pattern conditions said corresponding subset of interrupt signals by forcing interrupt signals at said plurality of interrupt inputs and complements of said interrupt signals at said plurality of interrupt inputs to a logical 1.

Claim 15

The circuitry of claim 1, wherein said signals at said plurality of interrupt inputs have identical priorities.

Claim 16

The circuitry of claim 1, wherein: (a) said interrupt mode select signal from said interrupt mode select selects said function from the group consisting a logical AND function, a logical OR function, and any combination thereof.

Claim 17

The circuitry of claim 3, wherein said mask register bit pattern is utilized by said combinatorial logic to compute said function in part.

Claim 18

The circuitry of claim 1, wherein said interrupt signals and said interrupt mode select signal have only two states.

Claim 19

The circuitry of claim 1, further wherein said interrupt mode select signal from said interrupt mode select selects said function is changeable.

Claim 20

Interrupt circuitry for a processor, comprising: (a) a plurality of interrupt inputs; (b) an interrupt output; (c) combinatorial logic with a plurality of combinatorial logic inputs connected to said plurality of interrupt inputs and with a combinatorial logic output connected to said interrupt output wherein an interrupt output signal at said combinatorial logic output is a function of interrupt signals at said plurality of combinatorial logic inputs; and (d) an interrupt mode select connected to said combinatorial logic wherein an interrupt mode select signal from said interrupt mode select controls said function.

Claim 21

Interrupt circuitry for a processor, comprising: (a) a plurality of interrupt inputs; (b) an interrupt output; (c) combinatorial logic with a plurality of combinatorial logic inputs connected to said plurality of interrupt inputs and with a combinatorial logic output connected to said interrupt output wherein an interrupt output signal at said combinatorial logic output is a function of interrupt signals at said plurality of combinatorial logic inputs; and (d) an interrupt mode select connected to said combinatorial logic wherein an interrupt mode select signal from said interrupt mode select controls said function.

Claim 22

The circuitry of claim 18, wherein: (a) said interrupt mode select signal from said interrupt mode select selects said function to be either AND or OR.

Claim 23

The circuitry of claim 18, further comprising: (a) a mask register having a plurality of mask register inputs and a plurality of mask register outputs, said plurality of mask register inputs connected to said plurality of interrupt inputs and said plurality of mask register outputs connected to said plurality of combinatorial logic inputs wherein a mask register bit pattern in said mask register conditions a corresponding subset (possibly empty) of said interrupt signals at said plurality of interrupt inputs to make said function and said interrupt output signal at said interrupt output not depend upon said corresponding subset.