Electrically erasable programmable read-only memory with write/verify controller

Claim 2

A non-volatile semiconductor memory system comprising: a memory cell array including rows and columns of electrically erasable and programmable memory cell transistors; write means for selecting from said memory cell transistors a first sub-array of memory cell transistors corresponding to one page, and for programming the first sub-array; write-verify means for verifying the electrical written state of the selected memory cell transistors by checking their threshold values for variations, and for, when any insufficiently written cell transistor remains among them, repeating a rewrite operation using a predetermined voltage for a predetermined period of time so that the written state comes closer to a satisfiable state; and said write-verify means comprising means for counting repetitions of the rewrite operation performed on said first sub-array of memory cell transistors until said written state is sufficiently close to said satisfiable state, producing a count value corresponding to the number of times that said rewrite operation is repeated until said satisfiable state is attained, and employing said count value in executing a write operation for a second sub-array of memory cell transistors corresponding to a second page such that the write operation executed for said second sub-array is automatically repeated a fixed number of times corresponding to said count value.

Claim 3

A system according to claim 1, wherein said write-verify means performs each rewrite operation by applying said voltage to the insufficient cell transistor for a predetermined period of time.

Claim 4

A system according to claim 2, wherein said write-verify means repeats the rewrite operation on said insufficient cell transistor until the written state reaches the satisfiable state.

Claim 5

A system according to claim 2, wherein said write-verify means repeats the rewrite operation on said insufficient cell transistor in the range of a preselected number of times.

Claim 6

A system according to claim 1, wherein each of said memory cell transistors includes a gate-insulated field effect transistor having an insulated carrier-storage layer, which is selectively charged or discharged by allowing charge carriers to flow into or from the carrier-storage layer, thereby changing the threshold value of the field effect transistor.

Claim 7

A system according to claim 5, further comprising: first insulated parallel lines associated with either ones of said rows and columns of memory cell transistors, for serving as data transfer lines; second insulated parallel lines associated with the remaining ones of said rows and columns of memory cell transistors, for functioning as program lines; and said sub-array forming one page including those memory cell transistors associated with one of said second lines.

Claim 8

A system according to claim 6, wherein said field effect transistor includes a floating-gate tunneling metal insulator semiconductor transistor.

Claim 9

A device according to claim 1, wherein said write-verify means is mounted on a separate semiconductor integrated circuit chip substrate.

Claim 10

A device according to claim 8, wherein said chip substrate is built in a card-shaped solid-state portable structure.

Claim 11

A device according to claim 9, wherein said electrically erasable and programmable memory cell transistor includes a floating-gate tunneling metal oxide semiconductor field effect transistor.

Claim 12

An electrically erasable and programmable read-only memory device comprising: a semiconductive substrate; an array of rows and columns of memory cells on said substrate, each of said memory cells including an insulated-gate transistor with a carrier-storage layer, said memory cells being divided into a plurality of cell groups each of which includes a series array of memory cells; data transfer lines associated with columns of memory cells; control lines insulatively crossing said data transfer lines above said substrate, and being associated with the rows of memory cells; program means connected to said control lines, for selecting a first of said control lines, and for simultaneously programming selected memory cells associated with the selected first control line in accordance with data bits supplied from those of said data transfer lines connected to said selected memory cells; write-verify means for verifying the electrical write state of said selected memory cells by checking threshold values of said selected memory cells for variations, and for, when any insufficiently written memory cells remains among said selected memory cells, performing a rewrite operation by additionally programming the insufficiently written memory cell using a predetermined write voltage and then rechecking the resulting write state so that the write state of said insufficiently written memory cell comes closer to a reference state, and for repeating said rewrite operation if the resulting write state does not come sufficiently close to said reference state; storage means associated with said write-verify means, for detecting the total number of the rewrite operations performed with respect to the insufficiently written memory cell, and for storing said total number as a program execution number; and write adjuster means connected to said storage means and said write-verify means, for when a second control line is selected, and if an insufficiently written memory cell is found, supplying said program execution number to said write-verify means, and for forcing said write-verify means to perform the rewrite operation for the insufficiently written memory cell.

Claim 13

An electrically erasable and programmable read-only memory device comprising: a semiconductive substrate; an array of rows and columns of memory cells on said substrate, each of said memory cells including an insulated-gate transistor with a carrier-storage layer, said memory cells being divided into a plurality of cell groups each of which includes a series array of memory cells; data transfer lines associated with columns of memory cells; control lines insulatively crossing said data transfer lines above said substrate, and being associated with the rows of memory cells; program means connected to said control lines, for selecting a first of said control lines, and for simultaneously programming selected memory cells associated with the selected first control line in accordance with data bits supplied from those of said data transfer lines connected to said selected memory cells; write-verify means for verifying the electrical write state of said selected memory cells by checking threshold values of said selected memory cells for variations, and for, when any insufficiently written memory cells remains among said selected memory cells, performing a rewrite operation by additionally programming the insufficiently written memory cell using a predetermined write voltage and then rechecking the resulting write state so that the write state of said insufficiently written memory cell comes closer to a reference state, and for repeating said rewrite operation if the resulting write state does not come sufficiently close to said reference state; storage means associated with said write-verify means, for detecting the total number of the rewrite operations performed with respect to the insufficiently written memory cell, and for storing said total number as a program execution number; and write adjuster means connected to said storage means and said write-verify means, for when a second control line is selected, and if an insufficiently written memory cell is found, supplying said program execution number to said write-verify means, and for forcing said write-verify means to perform the rewrite operation for the insufficiently written memory cell.

Claim 14

A device according to claim 11, wherein said write-verify means performs the rewrite operation by applying the write voltage to the insufficient cell for a predetermined period of time.

Claim 15

A device according to claim 11, wherein said write-verify means repeats a combination of a rewrite operation and a verify operation in the range of a predetermined number of times until said insufficient cell reaches the reference state.

Claim 16

A device according to claim 11, wherein said write-verify means and said write adjuster means are mounted on a separate semiconductor integrated circuit chip substrate.

Claim 17

A device according to claim 14, wherein said chip substrate is built in a card-shaped solid-state portable structure.

Claim 18

A device according to claim 15, wherein said insulated-gate transistor includes a floating-gate tunneling metal oxide semiconductor field effect transistor.

Claim 19

A non-volatile semiconductor memory system comprising: a memory cell array including rows and columns of electrically erasable and programmable memory cell transistors; write means for selecting from said memory cell transistors a first sub-array of memory cell transistors corresponding to one page, and for programming the first subarray; write-verify means for verifying the electrical written state of the selected memory cell transistors by checking their threshold values for variations, and for, when any insufficiently written cell transistor remains among them, repeating a rewrite operation using a predetermined voltage for a predetermined period of time so that the written state comes closer to a satisfiable state; and said write-verify means comprising means for counting repetitions of the rewrite operation performed on said first sub-array of memory cell transistors until said written state is sufficiently close to said satisfiable state, producing a count value corresponding to the number of times said rewrite operation is repeated until said satisfiable state is attained, and employing said count value in executing the write operation for a second sub-array of memory cell transistors corresponding to a second page such that the write operation executed for said second sub-array is automatically repeated a fixed number of times corresponding to said count value, the verify operations associated with said write-verify means being omitted during performing of said rewrite operations on said second sub-array of memory cell transistors.

Claim 20

A non-volatile semiconductor memory system comprising: a memory cell array including rows and columns of electrically erasable and programmable memory cell transistors; write means for selecting from said memory cell transistors a first sub-array of memory cell transistors corresponding to one page, and for programming the first subarray; write-verify means for verifying the electrical written state of the selected memory cell transistors by checking their threshold values for variations, and for, when any insufficiently written cell transistor remains among them, repeating a rewrite operation using a predetermined voltage for a predetermined period of time so that the written state comes closer to a satisfiable state; and said write-verify means comprising means for counting repetitions of the rewrite operation performed on said first sub-array of memory cell transistors until said written state is sufficiently close to said satisfiable state, producing a count value corresponding to the number of times said rewrite operation is repeated until said satisfiable state is attained, and employing said count value in executing the write operation for a second sub-array of memory cell transistors corresponding to a second page such that the write operation executed for said second sub-array is automatically repeated a fixed number of times corresponding to said count value, the verify operations associated with said write-verify means being omitted during performing of said rewrite operations on said second sub-array of memory cell transistors.

Claim 21

A device according to claim 17, wherein said write-verify means is mounted on a separate semiconductor integrated circuit chip substrate.

Claim 22

A device according to claim 18, wherein said chip substrate is built in a card-shaped-solid-state portable structure.

Claim 23

A device according to claim 19, wherein said electrically erasable and programmable memory cell transistor includes a floating-gate tunneling metal oxide semiconductor field effect transistor.