Speed controller of motor

Claim 2

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing, four or more memory values having a bit length shorter than that of said rotation error of said rotation error detection means or that of the control signal of said control signal generation means; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; synthetic error generation means for generating a synthetic error by synthesizing a plurality of said rotation errors of said rotation error detection means; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and control signal generation means for generating said control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 3

A speed controller of a motor according to claim 1, wherein said renewing and storing means further includes renewed value correction means for generating a renewed value by reducing the bit length of the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means, and said memory output value generation means includes memory output value correction means for making the bit length of said memory output value equal to the bit length of the rotation error.

Claim 4

A speed controller of a motor according to claim 2, wherein said renewed value correction means makes the value of the renewed value zero when the absolute value of the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means is greater than a predetermined value.

Claim 5

A speed controller of a motor according to claim 3, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 6

A speed controller of a motor according to claim 3, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 7

A speed controller of a motor according to claim 2, wherein said renewed value correction means changes the value of said renewed value to a value corresponding to a predetermined value when the absolute value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means is greater than a predetermined value.

Claim 8

A speed controller of a motor according to claim 6, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 9

A speed controller of a motor according to claim 6, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 10

A speed controller of a motor according to claim 1, wherein said renewing and storing means includes renewed value correction means for generating a renewed value by reducing the bit length of the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means, and said control signal generation means includes memory output value correction means for making the bit length of the memory output value equal to the bit length of the rotation error.

Claim 11

A speed controller of a motor according to claim 9, wherein said renewed value correction means makes the value of the renewed value zero when the absolute value of the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means is greater than a predetermined value.

Claim 12

A speed controller of a motor according to claim 10, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 13

A speed controller of a motor according to claim 10, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 14

A speed controller of a motor according to claim 9, wherein said renewed value correction means changes the value of said renewed value to a value corresponding to a predetermined value when the absolute value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means is greater than a predetermined value.

Claim 15

A speed controller of a motor according to claim 13, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 16

A speed controller of a motor according to claim 13, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 17

A speed controller of a motor according to claim 1, wherein said synthetic error generation means includes synthetic error correction means for generating a new synthetic error having a reduced bit length from said synthetic error, and said memory output value generation means includes memory output value correction means for making the bit length of said memory output value equal to the bit length of the rotation error.

Claim 18

A speed controller of a motor according to claim 16, wherein said synthetic error correction means makes the value of said new synthetic error zero when the absolute value of said synthetic error is greater than a predetermined value.

Claim 19

A speed controller of a motor according to claim 17, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 20

A speed controller of a motor according to claim 17, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 21

A speed controller of a motor according to claim 16, wherein said synthetic error correction means changes the value of said new synthetic error to a value corresponding to a predetermined value when the absolute value of said synthetic error is greater than a predetermined value.

Claim 22

A speed controller of a motor according to claim 20, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 23

A speed controller of a motor according to claim 20, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 24

A speed controller of a motor according to claim 1, wherein said synthetic error generation means includes synthetic error correction means for generating a new synthetic error having a reduced bit length from said synthetic error, and said control signal generation means includes memory output value correction means for making the bit length of said memory value equal to the bit length of the rotation error.

Claim 25

A speed controller of a motor according to claim 23, wherein said synthetic error correction means makes the value of said new synthetic error zero when the absolute value of said synthetic error is greater than a predetermined value.

Claim 26

A speed controller of a motor according to claim 24, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 27

A speed controller of a motor according to claim 24, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 28

A speed controller of a motor according to claim 23, wherein said synthetic error correction means changes the value of said new synthetic error to a value corresponding to a predetermined value when the absolute value of said synthetic error is greater than the predetermined value.

Claim 29

A speed controller of a motor according to claim 27, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 30

A speed controller of a motor according to claim 27, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 31

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which can be divided by a transmission function Ha(z -1 ) expressed by equation below: ##EQU13## [where z -1 is a delay of one sample time, and z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more)]; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and control signal generation means for generating a control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 32

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which can be divided by a transmission function Ha(z -1 ) expressed by equation below: ##EQU13## [where z -1 is a delay of one sample time, and z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more)]; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and control signal generation means for generating a control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 33

A speed controller of a motor according to claim 30, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 34

A speed controller of a motor according to claim 30, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 35

A speed controller of a motor according to claim 30, wherein P is equal to some multiples of Q.

Claim 36

A speed controller of a motor according to claim 33, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 37

A speed controller of a motor according to claim 33, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 38

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which can be use of a filter the transmission function of which can be divided by a transmission function Ha(z -1 ) expressed by equation below: ##EQU14## [where z -1 is a delay of one sample time, z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more), z -i is a delay of i sample time, and kf is a constant of an integer of 2 or more], renewing and storing means for renewing and storing substantially sequentially the memory value of the memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and control signal generation means for generating a control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 39

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which can be use of a filter the transmission function of which can be divided by a transmission function Ha(z -1 ) expressed by equation below: ##EQU14## [where z -1 is a delay of one sample time, z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more), z -i is a delay of i sample time, and kf is a constant of an integer of 2 or more], renewing and storing means for renewing and storing substantially sequentially the memory value of the memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and control signal generation means for generating a control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 40

A speed controller of a motor according to claim 36, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 41

A speed controller of a motor according to claim 36, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 42

A speed controller of a motor according to claim 36, wherein P is equal to some multiples of Q.

Claim 43

A speed controller of a motor according to claim 39, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 44

A speed controller of a motor according to claim 39, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 45

A speed controller of a motor according to claim 36, wherein P and kf are mutually different constants.

Claim 46

A speed controller of a motor according to claim 42, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 47

A speed controller of a motor according to claim 42, wherein said driving means includes low-pass filter means for reinforcing low frequency components of said control signal.

Claim 48

A speed controller of a motor according to claim 42, wherein P and kf are mutually different constants.

Claim 49

A speed controller of a motor according to claim 45, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 50

A speed controller of a motor according to claim 45, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 51

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes; rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which is expressed by equation below: ##EQU15## (where z -1 is a delay of one sample time, and z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more)]; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more ); and memory output value generation means and to the rotation error of said rotation error detection means.

Claim 52

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes; rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which is expressed by equation below: ##EQU15## (where z -1 is a delay of one sample time, and z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more)]; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more ); and memory output value generation means and to the rotation error of said rotation error detection means.

Claim 53

A speed controller of a motor according to claim 48, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 54

A speed controller of a motor according to claim 48, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 55

A speed controller of a motor according to claim 48, wherein P is equal to some multiples of Q.

Claim 56

A speed controller of a motor according to claim 51, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 57

A speed controller of a motor according to claim 51, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 58

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which is expressed by equation expressed below: ##EQU16## [where z -1 is a delay of one sample time, z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more), z -i is a delay of i sample time, and kf is a constant of an integer of 2 or more]; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is integer of 2 or more); and control signal generation means for generating a control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 59

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal on the basis of a detection signal of said speed detection means; and driving means for driving said motor in accordance with the control signal of said compensation means; wherein said compensation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; memory means for storing four or more memory values; memory output value generation means for generating a memory output value by the use of at least one memory value stored in said memory means; filter means for obtaining a calculation error from the rotation error of said rotation error detection means by the use of a filter the transmission function of which is expressed by equation expressed below: ##EQU16## [where z -1 is a delay of one sample time, z -P is a delay of P sample time (with the proviso that P is an integer of 2 or more), z -i is a delay of i sample time, and kf is a constant of an integer of 2 or more]; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the calculation error of said filter means and the memory output value of said memory output value generation means whenever said speed detection means effects the detection operation Q times (where Q is integer of 2 or more); and control signal generation means for generating a control signal responsive to the memory output value of said memory output value generation means and to the rotation error of said rotation error detection means.

Claim 60

A speed controller of a motor according to claim 54, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 61

A speed controller of a motor according to claim 54, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 62

A speed controller of a motor according to claim 54, wherein P is equal to some multiples to Q.

Claim 63

A speed controller of a motor according to claim 57, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 64

A speed controller of a motor according to claim 57, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 65

A speed controller of a motor according to claim 54, wherein P and kf are mutually different constants.

Claim 66

A speed controller of a motor according to claim 60, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 67

A speed controller of a motor according to claim 60, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 68

A speed controller of a motor according to claim 60, wherein P and kf are mutually different constants.

Claim 69

A speed controller of a motor according to claim 63, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 70

A speed controller of a motor according to claim 63, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 71

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal by first and second calculation means which operate substantially concurrently, in accordance with a detection signal of said speed detection means; and driving means for driving said motor in accordance with said control signal of said compensation means; wherein said first calculation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; control signal generation means for generating said control signal by calculating and synthesizing a memory output value produced by said second calculation means and the rotation error of said rotation error detection means; and operation timing generation means for generating a timing signal of said second calculation means; and wherein said second calculation means includes: memory means for storing four or more memory values; memory output value generation means for generating said memory Output value by the use of at least one memory value stored in said memory means; synthetic error generation means for generating a synthetic error by synthesizing a plurality of rotation errors of said rotation error detection means; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and operation management means for effecting the operation of said second calculation means by the timing signal of said operation timing generation means.

Claim 72

A speed controller of a motor comprising: rotation sensor means for generating an A.C. signal having a period in accordance with a rotating speed of a motor; speed detection means for effecting detection of the rotating speed of said motor a plurality of times per each revolution of said motor by using the A.C. signal of said rotation sensor means; compensation means for generating a control signal by first and second calculation means which operate substantially concurrently, in accordance with a detection signal of said speed detection means; and driving means for driving said motor in accordance with said control signal of said compensation means; wherein said first calculation means includes: rotation error detection means for obtaining a rotation error responsive to the detection signal of said speed detection means; control signal generation means for generating said control signal by calculating and synthesizing a memory output value produced by said second calculation means and the rotation error of said rotation error detection means; and operation timing generation means for generating a timing signal of said second calculation means; and wherein said second calculation means includes: memory means for storing four or more memory values; memory output value generation means for generating said memory Output value by the use of at least one memory value stored in said memory means; synthetic error generation means for generating a synthetic error by synthesizing a plurality of rotation errors of said rotation error detection means; renewing and storing means for renewing and storing substantially sequentially the memory value of said memory means by a renewed value corresponding to the value obtained by calculating and synthesizing the memory output value of said memory output value generation means and the synthetic error of said synthetic error generation means whenever said speed detection means effects the detection operation Q times (where Q is an integer of 2 or more); and operation management means for effecting the operation of said second calculation means by the timing signal of said operation timing generation means.

Claim 73

A speed controller of a motor according to claim 66, wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 74

A speed controller of a motor according to claim 66, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means changes the content of said second address generation means of said second calculation means in accordance with the timing signal generated by said operation timing generation means of said first calculation means to the address which is in advance set, so as to effect the operation of said second calculation means.

Claim 75

A speed controller of a motor according to claim 68, wherein said first memory means and said second memory means are used in common between said first calculation means and said second calculation means.

Claim 76

A speed controller of a motor according to claim 68, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 77

A speed controller of a motor according to claim 68, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 78

A speed controller of a motor according to claim 68, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means includes monitor means for monitoring a timing signal of said operation timing generation means of said first calculation means.

Claim 79

A speed controller of a motor according to claim 72, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 80

A speed controller of a motor according to claim 72, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 81

A speed controller of a motor according to claim 72, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 82

A speed controller of a motor according to claim 66, wherein said control signal generation means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 83

A speed controller of a motor according to claim 76, wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 84

A speed controller of a motor according to claim 76, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means changes the content of said second address generation means of said second calculation means in accordance with the timing signal of said operation timing generation means of said first calculation means to the address which is set in advance, so as to effect the operation of said second calculation means.

Claim 85

A speed controller of a motor according to claim 78, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 86

A speed controller of a motor according to claim 78, wherein said first digital value memory means and second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 87

A speed controller of a motor according to claim 78, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 88

A speed controller of a motor according to claim 76, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address Generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 89

A speed controller of a motor according to claim 82, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 90

A speed controller of a motor according to claim 82, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 91

A speed controller of a motor according to claim 82, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 92

A speed controller of a motor according to claim 66, wherein said driving means includes low-pass reinforcing filter means for reinforcing low frequency components of said control signal.

Claim 93

A speed controller of a motor according to claim 86, wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 94

A speed controller of a motor according to claim 86, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means changes the content of said second address generation means of said second calculation means in accordance with the timing signal of said operation timing generation means of said first calculation means to the address which is set in advance, so as to effect the operation of said second calculation means.

Claim 95

A speed controller of a motor according to claim 88, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 96

A speed controller of a motor according to claim 88, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 97

A speed controller of a motor according to claim 88, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 98

A speed controller of a motor according to claim 86, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 99

A speed controller of a monitor according to claim 92, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 100

A speed controller of a motor according to claim 92, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 101

A speed controller of a motor according to claim 92, wherein said first calculation execution means and second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 102

A speed controller of a motor according to claim 66, wherein said low-pass reinforcing filter means for reinforcing low frequency components of said control signal includes: integration means for integrating said control signals and generating an integrated control signal; and filter synthesis means for adding a value corresponding to said integrated control signal to said control signal and generating a new control signal; wherein said first calculation means includes: said filter synthesis means; and wherein said second calculation means includes; said integration means.

Claim 103

A speed controller of a motor according to claim 96, wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 104

A speed controller of a motor according to claim 96, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operations; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means is effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means changes the content of said second address generation means of said second calculation means in accordance with the timing signal of said operation timing generation means of said first calculation means to a value which is set in advance, so as to effect the operation of said calculation means.

Claim 105

A speed controller of a motor according to claim 98, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 106

A speed controller of a motor according to claim 98, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 107

A speed controller of a motor according to claim 98, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.

Claim 108

A speed controller of a motor according to claim 96, wherein the operation of said first calculation means is effected by: first instruction memory means storing therein in advance a series of calculation operation; first digital value memory means storing therein a plurality of digital values; first address generation means for generating the address of said first instruction memory means; and first calculation execution means for effecting the operation of said first calculation means in accordance with the instruction stored in said first instruction memory means; wherein the operation of said second calculation means in effected by: second instruction memory means storing therein in advance a series of calculation operations; second digital value memory means storing therein a plurality of digital values; second address generation means for generating the address of said second instruction memory means; and second calculation execution means for effecting the operation of said second calculation means in accordance with the instruction stored in said second instruction memory means; and wherein said operation management means of said second calculation means includes monitor means for monitoring the timing signal of said operation timing generation means of said first calculation means.

Claim 109

A speed controller of a motor according to claim 102, wherein said first instruction memory means and said second instruction memory means are used in common between said first calculation means and said second calculation means.

Claim 110

A speed controller of a motor according to claim 102, wherein said first digital value memory means and said second digital value memory means are used in common between said first calculation means and said second calculation means.

Claim 111

A speed controller of a motor according to claim 102, wherein said first calculation execution means and said second calculation execution means are used in common between said first calculation means and said second calculation means.