US5374904A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked-loop circuit having adjustable reference clock signal frequency and filter capacitance compensation
Assignee: Renesas Electronics Corp
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Filing: 1993-06-22
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Granted: 1994-12-20
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Expires: 2013-06-22
Abstract
Abstract A phase synchronization circuit including a phase-locked-loop synchronizes a phase of a clock signal with a phase of a reference clock signal having a frequency desired by a user. The gates of an NMOS transistor and a PMOS transistors are connected in common to a resistor. The drain and the source of the NMOS transistor are both connected to a ground potential while the drain and the source of the PMOS transistor are both connected to a power source voltage. By changing a number of NMOS and PMOS transistors formed during a metallization process, the capacitance in a loop filter is easily changed.
Inventors
- 👤 Atsuhiko Ishibashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:24
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
343 words
A phase synchronization circuit for synchronizing the phase of a clock signal to that of a reference clock signal, said phase synchronization circuit comprising: clock signal generating means having an input terminal and at least one output terminal, said clock signal generating means generating a clock signal in accordance with a potential received at said input terminal and supplying said clock signal to said at least one output terminal; electric charge generating means, having a first input terminal connected to receive said clock signal and a second input terminal for receiving a reference clock signal, for generating an electric charge corresponding to a difference in phase between said clock signal and said reference clock signal; and potential generating means, having an input terminal connected to receive said electric charge output from said electric charge generating means and an output terminal for outputting a potential corresponding to said electric charge to said clock signal generating means, said clock signal generating means, said electric charge generating means, and said potential generating means thereby forming a phase-locked loop, wherein said potential generating means comprises a first potential terminal for supplying a first potential; a second potential terminal for supplying a second potential which is lower than said first potential; at least one first insulated gate capacitor, each one of said at least one first insulated gate capacitor having an n type semiconductor layer connected to said first potential terminal, an insulating layer formed on said n type semiconductor layer, and a gate electrode formed adjacent to and facing said insulating layer; at least one second insulated gate capacitor, each one of said at least one second insulated gate capacitor having a p type semiconductor layer connected to said second potential terminal, an insulating layer formed on said p type semiconductor layer, and a gate electrode formed adjacent to and facing said insulating layer; and a resistor having one terminal thereof connected to said input terminal of said potential generating means and having the other terminal thereof connected to said output terminal of said potential generating means.
Claim 2
Dependent Claim
343 words
A phase synchronization circuit for synchronizing the phase of a clock signal to that of a reference clock signal, said phase synchronization circuit comprising: clock signal generating means having an input terminal and at least one output terminal, said clock signal generating means generating a clock signal in accordance with a potential received at said input terminal and supplying said clock signal to said at least one output terminal; electric charge generating means, having a first input terminal connected to receive said clock signal and a second input terminal for receiving a reference clock signal, for generating an electric charge corresponding to a difference in phase between said clock signal and said reference clock signal; and potential generating means, having an input terminal connected to receive said electric charge output from said electric charge generating means and an output terminal for outputting a potential corresponding to said electric charge to said clock signal generating means, said clock signal generating means, said electric charge generating means, and said potential generating means thereby forming a phase-locked loop, wherein said potential generating means comprises a first potential terminal for supplying a first potential; a second potential terminal for supplying a second potential which is lower than said first potential; at least one first insulated gate capacitor, each one of said at least one first insulated gate capacitor having an n type semiconductor layer connected to said first potential terminal, an insulating layer formed on said n type semiconductor layer, and a gate electrode formed adjacent to and facing said insulating layer; at least one second insulated gate capacitor, each one of said at least one second insulated gate capacitor having a p type semiconductor layer connected to said second potential terminal, an insulating layer formed on said p type semiconductor layer, and a gate electrode formed adjacent to and facing said insulating layer; and a resistor having one terminal thereof connected to said input terminal of said potential generating means and having the other terminal thereof connected to said output terminal of said potential generating means.
Claim 3
Dependent Claim
61 words
The phase synchronization circuit according to claim 1, wherein said clock signal generating means further comprises first processing means for generating a basic signal which has a frequency corresponding to a potential which is received at said input terminal of said clock signal generating means, and second processing means for generating said clock signal on the basis of said basic signal.
Claim 4
Dependent Claim
130 words
The phase synchronization circuit according to claim 1, wherein said electric charge generating means includes: a phase frequency comparator for outputting first phase information and second phase information, said first phase information indicating whether a phase of said clock signal which is supplied to said output terminal of said clock signal generating means lags or leads a phase of said reference clock signal, said second phase information having a pulse width which corresponds to a phase difference between a phase of said clock signal which is supplied to said output terminal of said clock signal generating means and a phase of said reference clock signal; and a charge pump circuit, having input terminals connected to receive said first phase information and said second phase information, for generating said electric charge.
Claim 5
Dependent Claim
26 words
The phase synchronization circuit according to claim 1, wherein said at least one first insulated gate capacitor comprises a plurality of said first insulated gate capacitors.
Claim 6
Dependent Claim
26 words
The phase synchronization circuit according to claim 1, wherein said at least one second insulated gate capacitor comprises a plurality of said second insulated gate capacitors.
Claim 7
Dependent Claim
43 words
The phase synchronization circuit according to claim 1, wherein each one of said at least one first insulated gate capacitor includes a p type insulated gate field effect transistor having two current electrodes, both of which are connected to said first potential terminal.
Claim 8
Dependent Claim
43 words
The phase synchronization circuit according to claim 1, wherein each one of said at least one second insulated gate capacitor includes an n type insulated gate field effect transistor having two current electrodes, both of which are connected to said second potential terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |