Dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators

Claim 2

A maximum likelihood detector for a continuous time, disk drive read channel, comprising: a dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators for detecting the positive and negative peaks of an input signal; comparator means for comparing said input signal with at least one present dynamic threshold to produce positive and negative binary gating signals; a control circuit responsive to said binary gating signals, the input signal, and said peak detector circuit for identifying qualified input signal peaks: and a threshold update circuit, responsive to the identification of an input signal peak, for adjusting the present dynamic threshold by the difference between the input signal and the present dynamic threshold to obtain the next dynamic threshold.

Claim 3

The maximum likelihood detector for a continuous time, disk drive read channel of claim 1 in which said threshold update circuit includes: a positive summing circuit for comparing said input signal with a combination of a predetermined positive threshold and said at least one present dynamic threshold to obtain the difference; a negative summing circuit for comparing said input signal with a combination of a predetermined negative threshold and said at least one present dynamic threshold to obtain the difference; an adder circuit selectively responsive to one of said summing circuits and said present dynamic threshold to generate an updated dynamic threshold: and a holding circuit responsive to said updated dynamic threshold producing the next present dynamic threshold.

Claim 4

The maximum likelihood detector for a continuous time, disk drive read channel of claim 1 in which said threshold update circuit includes: a positive summing circuit for comparing the combination of said input signal and a negative threshold with a said at least one present dynamic threshold to obtain the difference; a negative summing circuit for comparing the combination of said input signal and a positive threshold with a said at least one present dynamic threshold to obtain the difference; an adder circuit selectively responsive to one of said summing circuits and said present dynamic threshold to generate an updated dynamic threshold: and a holding circuit responsive to said updated dynamic threshold for producing the next present dynamic threshold.

Claim 5

A dynamic threshold updating circuit for a maximum likelihood detector for a continuous time, disk drive read channel, comprising: a positive summing circuit for comparing an input signal with a combination of a predetermined positive threshold and at least one present dynamic threshold to obtain the difference; a negative summing circuit for comparing said input signal with a combination of a predetermined negative threshold and at least one present dynamic threshold to obtain the difference; an adder circuit selectively responsive to one of said summing circuits and said present dynamic threshold to generate an updated dynamic threshold; and a holding circuit responsive to said updated dynamic threshold for producing the next present dynamic threshold.

Claim 6

A dynamic threshold updating circuit for a maximum likelihood detector for a continuous time, disk drive read channel, comprising: a positive summing circuit for comparing an input signal with a combination of a predetermined positive threshold and at least one present dynamic threshold to obtain the difference; a negative summing circuit for comparing said input signal with a combination of a predetermined negative threshold and at least one present dynamic threshold to obtain the difference; an adder circuit selectively responsive to one of said summing circuits and said present dynamic threshold to generate an updated dynamic threshold; and a holding circuit responsive to said updated dynamic threshold for producing the next present dynamic threshold.

Claim 7

The dynamic threshold updating circuit of claim 4 in which said positive and negative summing circuits each includes an adder for combining said present dynamic threshold with said positive and negative thresholds, respectively.

Claim 8

The dynamic threshold updating circuit of claim 4 in which said adder circuit includes an adder device and switching means for selectively providing the difference output from said positive and negative summing circuits to said adder device for combining with said present dynamic threshold.

Claim 9

The dynamic threshold updating circuit of claim 4 in which said holding circuit includes a sample and hold circuit.

Claim 10

The dynamic threshold updating circuit of claim 4 in which said holding circuit includes a track and hold circuit.

Claim 11

A maximum likelihood detector for a continuous time, disk drive read channel comprising: a positive comparator circuit for comparing an input signal with a combination of a predetermined positive threshold and a present dynamic threshold to produce a positive binary gating signal; a negative comparator circuit for comparing an input signal with a combination of a predetermined negative threshold and a present dynamic threshold to produce a negative binary gating signal; a peak detection circuit; a control circuit responsive to said peak detector circuit for providing qualified input signal peaks upon the coincidence of the detection of a peak signal by said peak detector circuit and a gating signal from one of said comparator circuits; said control circuit including a positive summing circuit for comparing said input signal with a combination of a predetermined positive threshold and said at least one present dynamic threshold to obtain the difference; a negative summing circuit for comparing said input signal with a combination of a predetermined negative threshold and said at least one present dynamic threshold to obtain the difference; an adder circuit selectively responsive to one of said summing circuits and said present dynamic threshold to generate an updated dynamic threshold; and a holding circuit responsive to said updated dynamic threshold for producing the next present dynamic threshold.

Claim 12

A maximum likelihood detector for a continuous time, disk drive read channel comprising: a positive comparator circuit for comparing an input signal with a combination of a predetermined positive threshold and a present dynamic threshold to produce a positive binary gating signal; a negative comparator circuit for comparing an input signal with a combination of a predetermined negative threshold and a present dynamic threshold to produce a negative binary gating signal; a peak detection circuit; a control circuit responsive to said peak detector circuit for providing qualified input signal peaks upon the coincidence of the detection of a peak signal by said peak detector circuit and a gating signal from one of said comparator circuits; said control circuit including a positive summing circuit for comparing said input signal with a combination of a predetermined positive threshold and said at least one present dynamic threshold to obtain the difference; a negative summing circuit for comparing said input signal with a combination of a predetermined negative threshold and said at least one present dynamic threshold to obtain the difference; an adder circuit selectively responsive to one of said summing circuits and said present dynamic threshold to generate an updated dynamic threshold; and a holding circuit responsive to said updated dynamic threshold for producing the next present dynamic threshold.

Claim 13

The maximum likelihood detector for a continuous time, disk drive read channel of claim 8 in which said positive and negative comparator circuits each include an adder system for combining said present dynamic threshold with said positive and negative thresholds.

Claim 14

Maximum likelihood detector for a continuous time, disk drive read channel of claim 9 in which said peak detection circuit includes a differentiator circuit for generating zero crossings at the peaks of the input signal and a zero crossing detection circuit for detecting those zero crossings at the peak.