Patent US3356415A successfully refreshed from Google Patents.
US5372971A
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US
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Method for forming via hole in multiple metal layers of semiconductor device
Assignee: SK Hynix Inc
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Filing: 1992-10-01
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Granted: 1994-12-13
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Expires: 2012-10-01
Abstract
Abstract A method for forming a via hole in multiple metal layers of the semiconductor device is disclosed. In a via hole forming process of the semiconductor device, a barrier layer is formed beneath the photoresistive layer. Accordingly, the polymer residue formed on the metal-layer pattern and side wall of the via hole is prevented during the plasma etching process.
Inventors
- 👤 Mi Young Kang
- 👤 Gon Son
- 👤 Jin Ki Jung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:48
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W20/00; H10W20/01; H10W20/031
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
171 words
A method for forming a via hole in multiple metal layers of semiconductor device, comprising the steps of: depositing a first insulating layer on a silicon substrate; forming a metal layer pattern on said first insulating layer; depositing a second insulating layer on said metal layer pattern; forming a barrier layer on said second insulating layer; coating a photoresist layer on said barrier layer; forming a slot by etching away the determined portion of the photoresist layer; removing the portion of the exposed barrier layer thereunder and a portion of the second insulating layer thereunder by etching wherein the remaining unetched portion of the second insulating layer covers the portion of the metal layer facing the slot to prevent exposure of the metal layer via the slot; removing the remaining photoresist layer; forming a via hole by etching away the remaining portion of the second insulating layer using said barrier layer as a mask; and depositing a conductive layer over said via hole to thereby contact with said metal layer pattern.
Claim 2
Independent Claim
171 words
A method for forming a via hole in multiple metal layers of semiconductor device, comprising the steps of: depositing a first insulating layer on a silicon substrate; forming a metal layer pattern on said first insulating layer; depositing a second insulating layer on said metal layer pattern; forming a barrier layer on said second insulating layer; coating a photoresist layer on said barrier layer; forming a slot by etching away the determined portion of the photoresist layer; removing the portion of the exposed barrier layer thereunder and a portion of the second insulating layer thereunder by etching wherein the remaining unetched portion of the second insulating layer covers the portion of the metal layer facing the slot to prevent exposure of the metal layer via the slot; removing the remaining photoresist layer; forming a via hole by etching away the remaining portion of the second insulating layer using said barrier layer as a mask; and depositing a conductive layer over said via hole to thereby contact with said metal layer pattern.
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein said metal layer pattern is selected from the group consisting of aluminum, an alloy of aluminum and copper.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein said barrier layer is selected from the group consisting of TiN, Ti, and TiW.
Claim 5
Independent Claim
173 words
A method for forming a via hole in multiple metal layers of semiconductor device, comprising the steps of: depositing a first insulating layer on a silicon substrate: forming a metal layer pattern on said first insulating layer; depositing a second insulating layer on said metal layer pattern; forming a metal barrier layer on said second insulating layer; coating a photoresist layer on said metal barrier layer; forming a slot by etching away the determined portion of the photoresist layer; removing the portion of the exposed barrier layer thereunder and a portion of the second insulating layer thereunder by etching wherein the remaining unetched portion of the second insulating layer covers the portion of the metal layer facing the slot to prevent exposure of the metal layer via the slot; removing the remaining photoresist layer; forming a via hole by etching away the remaining portion of the second insulating layer, using said barrier layer as a mask: and depositing a conductive layer over said via hole to thereby contact with said metal layer pattern.
Claim 6
Independent Claim
173 words
A method for forming a via hole in multiple metal layers of semiconductor device, comprising the steps of: depositing a first insulating layer on a silicon substrate: forming a metal layer pattern on said first insulating layer; depositing a second insulating layer on said metal layer pattern; forming a metal barrier layer on said second insulating layer; coating a photoresist layer on said metal barrier layer; forming a slot by etching away the determined portion of the photoresist layer; removing the portion of the exposed barrier layer thereunder and a portion of the second insulating layer thereunder by etching wherein the remaining unetched portion of the second insulating layer covers the portion of the metal layer facing the slot to prevent exposure of the metal layer via the slot; removing the remaining photoresist layer; forming a via hole by etching away the remaining portion of the second insulating layer, using said barrier layer as a mask: and depositing a conductive layer over said via hole to thereby contact with said metal layer pattern.
Claim 7
Dependent Claim
24 words
The method of claim 4, wherein said metal layer pattern is selected from the group consisting of aluminum, an alloy of aluminum and copper.
Claim 8
Dependent Claim
21 words
The method of claim 4, wherein said metal barrier layer is selected from the group consisting of TiN, Ti, and TiW.
Claim 9
Dependent Claim
32 words
The method of claim 1, wherein the step of removing the portion of the exposed barrier layer and the portion of the second insulating layer thereunder is by a plasma etching method.
Claim 10
Dependent Claim
32 words
The method of claim 4, wherein the step of removing the portion of the exposed barrier layer and the portion of the second insulating layer thereunder is by a plasma etching method.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |