US5369604A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test plan generation for analog integrated circuits
Assignee: Texas Instruments Inc
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Filing: 1993-02-05
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Granted: 1994-11-29
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Expires: 2013-02-05
Abstract
Abstract A method of generating a test plan for a circuit designed with blocks of analog, digital, or mixed signal components. Each block is treated as a separate functional unit, with a test having block inputs that are set to predetermined values. A matrix of circuit equations is set up to determine what circuit inputs will result in these block inputs. The required number of equations is obtained by identifying any circuit inputs that need to be set heuristically.
Inventors
- 👤 Naiknaware Ravindranath
- 👤 G. N. Nandakumar
- 👤 Kasa S. Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/3167; G01R31/317; G01R31/31707
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
224 words
A method of using a computer to automatically generate a test plan for an integrated circuit comprised of blocks of analog or mixed signal components, wherein the number of unknown circuit voltages and currents is greater than the number of available circuit equations, comprising the steps of: loading a block functional description of the circuit into a computer; loading predefined block test models for each block of the integrated circuit into the computer; setting each functional blocks' inputs to values specified by the predefined block test model for them; automatically determining by the computer whether a sufficient number of block inputs are set by said setting step, such that the number of unknown circuit voltages and currents is the same as the number of available circuit equations; if said number of inputs is not sufficient, automatically identifying by the computer circuit pins to be set with a known voltage value; automatically setting by the computer each circuit pin identified during said identifying step with a voltage value; automatically forming a matrix of circuit equations by the computer whose unknown variables include voltages at those circuit pins not identified in said identifying step; automatically solving said matrix for said unknown variables by the computer; and listing values provided by said solving step as circuit input values to be applied during a test of said block.
Claim 2
Independent Claim
224 words
A method of using a computer to automatically generate a test plan for an integrated circuit comprised of blocks of analog or mixed signal components, wherein the number of unknown circuit voltages and currents is greater than the number of available circuit equations, comprising the steps of: loading a block functional description of the circuit into a computer; loading predefined block test models for each block of the integrated circuit into the computer; setting each functional blocks' inputs to values specified by the predefined block test model for them; automatically determining by the computer whether a sufficient number of block inputs are set by said setting step, such that the number of unknown circuit voltages and currents is the same as the number of available circuit equations; if said number of inputs is not sufficient, automatically identifying by the computer circuit pins to be set with a known voltage value; automatically setting by the computer each circuit pin identified during said identifying step with a voltage value; automatically forming a matrix of circuit equations by the computer whose unknown variables include voltages at those circuit pins not identified in said identifying step; automatically solving said matrix for said unknown variables by the computer; and listing values provided by said solving step as circuit input values to be applied during a test of said block.
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein said identifying step is performed by locating a circuit input that is farthest from the block under test.
Claim 4
Dependent Claim
22 words
The method of claim 1, further comprising the step of identifying circuit outputs to be measured during a test of said block.
Claim 5
Dependent Claim
38 words
The method of claim 1, wherein said matrix includes unknown circuit outputs and further comprising the step of listing values provided by said solving step as circuit output values to be expected during a test of said block.
Claim 6
Dependent Claim
22 words
The method of claim 1, further comprising the step of setting values to power pins of said circuit before said solving step.
Claim 7
Dependent Claim
31 words
The method of claim 5, wherein said identifying step is performed if the number of inputs with values set in said setting steps is less than the number of circuit inputs.
Claim 8
Dependent Claim
36 words
The method of claim 1, further comprising the step of identifying mixed signal blocks in said circuit and of setting values of at least one input and at least one output of said mixed signal block.
Claim 9
Dependent Claim
19 words
The method of claim 1, further comprising the step of identifying and masking any digital blocks in said circuit.
Claim 10
Dependent Claim
33 words
The method of claim 1, wherein said step of forming a matrix is accomplished by generating KCL equations for said circuit and at least one functional equation for each block of said circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-28 | 2006-05-30 | 2006-11-29 | $7700.00 | Window Closed / Lapsed |