Digital/analog converter circuit utilizing compensation circuitry

Claim 1

A digital/analog converter circuit comprising first to third transistors, said first transistor having a gate terminal for inputting a constant voltage and one side terminal for inputting a power source voltage, said second transistor having a gate terminal for inputting a first digital signal, one side terminal connected to the other side terminal of said first transistor and the other side terminal forming a first output terminal, said third transistor having a gate terminal for inputting a second digital signal of the opposite phase to that of the first digital signal, one side terminal connected to the other side terminal of said first transistor and the other side terminal forming a second output terminal, wherein the improvement comprises: buffer means for buffering a digital input signal and applying the buffered digital input signal as the second digital signal to the gate terminal of said third transistor; inverter means for inverting the digital input signal and applying the inverted digital input signal as the first digital signal to the gate terminal of said second transistor, said inverter means having first compensating means, said first compensating means removing an input transfer time difference between said second and third transistors in response to the buffered digital input signal from said buffer means; second compensating means for removing floating electrons from said inverter means in response to the digital input signal; and third compensating means for compensating for a poor "0" logical state transfer capability of said buffer means in response to the inverted digital input signal from said inverter means.