Voltage pumping circuit for semiconductor memory devices

Claim 2

A voltage pumping circuit in a semiconductor memory device provided with a source operating voltage and including an oscillator circuit for generating a series of pulses, said voltage pumping circuit comprising: input means for receiving said series of pulses from said oscillator circuit to generate a pair of complementary output signals; voltage pump means coupled to said input means and responsive to said series of pulses and said source operating voltage for generating at a voltage pumping node a first output voltage level, at an initial power-up state, and thereafter pumping the first output voltage level up to a second output voltage level when the semiconductor memory device is in active operational mode; detecting means coupled to said voltage pump means for detecting when the second voltage output voltage level has been reached to control the pumping operation of the voltage pump means so as to maintain the second output voltage level at the voltage pumping node; pumping means for generating at the voltage pumping node the second output voltage level in response to an output from said input means; and bias means coupled to said pumping means and responsive to the source operating voltage for forcing the first output voltage level at the voltage pumping node at the initial power-up state.

Claim 3

The voltage pumping circuit of claim 1, further comprising driving means for amplifying the complementary output signals from said input means.

Claim 4

The voltage pumping circuit of claim 2, wherein said pumping means comprises a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to amplified complementary output signals from said driving means.

Claim 5

The voltage pumping circuit of claim 3, wherein said pumping means further comprises first and second transmission transistors for providing the second output voltage level to said voltage pumping node by way of a charge sharing occurring through respective channels thereof, gates and selected first terminals of the channels of said first and second transmission transistors being respectively coupled to the second electrodes of said plurality of capacitors.

Claim 6

The voltage pumping circuit of claim 4, wherein said first and second transmission transistors are alternatively turned-on and turned-off in response to the pair of complementary output signals output from said input means.

Claim 7

The voltage pumping circuit of claim 4, wherein said bias means comprises: a first bias circuit for providing the source operating voltage to said first terminals of the respective channels of said first and second transmission transistors; and a second bias circuit for providing the source operating voltage to the respective gates of said first and second transmission transistors.

Claim 8

The voltage pumping circuit of claim 6, wherein said first and second bias circuits in association with each other provide the voltage pumping node with the first output voltage level at the initial power-up state.

Claim 9

A voltage pumping circuit provided with a supply voltage and including an oscillator which generates a series of pulses comprising: input means for receiving the series of pulses from said oscillator to generate a pair of complementary output signals; voltage pumping means for pumping up the voltage level of a signal output from said input means to generate a pumped voltage level at a voltage pumping node; bias means for selectively providing the supply voltage at the voltage pumping node detecting means coupled to said voltage pumping means for detecting when the pumped voltage level has been reached to control the pumping operation of the volt pumping means so as to maintain the pumped voltage level at the voltage pumping node.

Claim 10

A voltage pumping circuit provided with a supply voltage and including an oscillator which generates a series of pulses comprising: input means for receiving the series of pulses from said oscillator to generate a pair of complementary output signals; voltage pumping means for pumping up the voltage level of a signal output from said input means to generate a pumped voltage level at a voltage pumping node; bias means for selectively providing the supply voltage at the voltage pumping node detecting means coupled to said voltage pumping means for detecting when the pumped voltage level has been reached to control the pumping operation of the volt pumping means so as to maintain the pumped voltage level at the voltage pumping node.

Claim 11

The voltage pumping circuit of claim 8, wherein said voltage pumping means comprises a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to amplified complementary output signals from said input means.

Claim 12

The voltage pumping circuit of claim 9, wherein said voltage pumping means further comprises first and second diode-connected transmission transistors for providing the pumped voltage level to said voltage pumping node by way of a charge sharing occurring through respective channels thereof, gates and selected first terminals of the channels of said first and second transmission transistors being respectively coupled to the second electrodes of said plurality of capacitors.

Claim 13

The voltage pumping circuit of claim 10, wherein said first and second diode-connected transmission transistors are alternatively turned-on and turned-off in response to the pair of complementary output signals from said input means.

Claim 14

The voltage pumping circuit of claim 11, wherein said bias means provides the supply voltage to the first terminal of respective channels of said first and second diode-connected transmission transistors.

Claim 15

A voltage pumping circuit in a semiconductor memory device having an oscillator for generating a series of pulses comprising: input means for receiving the series of pulses from said oscillator to generate a pair of complementary output signals; driver means for amplifying output signals from said input means; voltage pumping means comprising a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to amplified output signals from said driving means; transmission means coupled to said second electrodes of said plurality of capacitors of said voltage pumping means for generating a pumped voltage at a voltage pumping node; and bias means for forcing a voltage, substantially identical to the source operating voltage, at the voltage pumping node at an initial power-up state.

Claim 16

A voltage pumping circuit in a semiconductor memory device having an oscillator for generating a series of pulses comprising: input means for receiving the series of pulses from said oscillator to generate a pair of complementary output signals; driver means for amplifying output signals from said input means; voltage pumping means comprising a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to amplified output signals from said driving means; transmission means coupled to said second electrodes of said plurality of capacitors of said voltage pumping means for generating a pumped voltage at a voltage pumping node; and bias means for forcing a voltage, substantially identical to the source operating voltage, at the voltage pumping node at an initial power-up state.

Claim 17

The voltage pumping circuit of claim 13, further comprising detecting means coupled to said voltage pumping means for detecting when the pumped voltage level has been reached to control the pumping operation of the voltage pumping means so as to maintain the pumped voltage level at the voltage pumping node.

Claim 18

A voltage pumping circuit in a semiconductor memory device having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied during active operational mode comprising: input means for receiving an enable input signal; voltage pumping means for generating said pumped voltage in response to an output from said input means, wherein if the voltage level of the pumped voltage drops during active operational mode, the voltage pumping means detects the voltage drop to raise the pumped voltage to a predetermined level; and output means for supplying the pumped voltage to said voltage pumping node; precharge means for precharging the output from said voltage pumping means to a voltage substantially identical to the supply voltage during non-active operational mode of the semiconductor memory device so as to increase the voltage pumping efficiency of said voltage pumping means.

Claim 19

A voltage pumping circuit in a semiconductor memory device having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied during active operational mode comprising: input means for receiving an enable input signal; voltage pumping means for generating said pumped voltage in response to an output from said input means, wherein if the voltage level of the pumped voltage drops during active operational mode, the voltage pumping means detects the voltage drop to raise the pumped voltage to a predetermined level; and output means for supplying the pumped voltage to said voltage pumping node; precharge means for precharging the output from said voltage pumping means to a voltage substantially identical to the supply voltage during non-active operational mode of the semiconductor memory device so as to increase the voltage pumping efficiency of said voltage pumping means.

Claim 20

The voltage pumping circuit of claim 15, wherein said voltage pumping circuit is enabled only during active operational mode of the semiconductor memory device.

Claim 21

The voltage pumping circuit of claim 15, wherein said voltage pumping means comprises at least one voltage pumping capacitor coupled to and responsive to the output of said input means.

Claim 22

The voltage pumping circuit of claim 15, wherein said precharge means comprises: at least one voltage pumping capacitor coupled to the output of said input means; and a plurality of pull-up transistors coupled between the voltage pumping capacitor and the pumped voltage output; whereby an initial output voltage of said voltage pumping means is precharged substantially identical to the supply voltage by the pull-up transistors during non-active operational mode of the semiconductor memory device.

Claim 23

The voltage pumping circuit of claim 15, wherein said enable input signal is one of a first signal generated in association with row or column address strobe signals and a second signal generated upon a power-up of the semiconductor memory device.

Claim 24

A voltage pumping circuit in a semiconductor memory device having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied during active operational mode comprising: input means for receiving an enable input signal; voltage pumping means for generating said pumped voltage in response to an output from said input means; precharge means coupled to the output of said input means for precharging a voltage at the voltage pumping node which is substantially identical to the supply voltage during non-active operational mode of the semiconductor memory device; output means for supplying the pumped voltage to the voltage pumping node during active operational mode of the semiconductor memory device; and control means for controlling operation of said output means in response to the output from said input means.

Claim 25

A voltage pumping circuit in a semiconductor memory device having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied during active operational mode comprising: input means for receiving an enable input signal; voltage pumping means for generating said pumped voltage in response to an output from said input means; precharge means coupled to the output of said input means for precharging a voltage at the voltage pumping node which is substantially identical to the supply voltage during non-active operational mode of the semiconductor memory device; output means for supplying the pumped voltage to the voltage pumping node during active operational mode of the semiconductor memory device; and control means for controlling operation of said output means in response to the output from said input means.

Claim 26

The voltage pumping circuit of claim 20, wherein said voltage pumping means comprises: a driver circuit coupled to the output of said input means; and a first voltage pumping capacitors having first and second electrodes, the first electrode being coupled to the output of said driver circuit and the second electrode being coupled to the precharge means.

Claim 27

The voltage pumping circuit of claim 21, wherein said precharge means comprises: a second voltage pumping capacitor having first and second electrodes, the first electrode being coupled to the output of said input means; a first pull-up transistor having its gate connected to the supply voltage and its channel connected between the supply voltage and the second electrode of said second voltage pumping capacitor; a second pull-up transistor having its gate connected to the voltage pumping node and its channel connected between the supply voltage and the second electrode of said second voltage pumping capacitor; a third pull-up transistor having its gate connected to the supply voltage and its channel connected between the supply voltage and an output of said voltage pumping means; and a fourth pull-up transistor with a gate connected to the second electrode of said second voltage pumping capacitor and a channel connected between the supply voltage and the output of said voltage pumping means.

Claim 28

The voltage pumping circuit of claim 21, wherein said control means comprises: a third voltage pumping capacitor having first and second electrodes, the first electrode being coupled to the output of said input means and the second electrode being coupled to a control terminal of said output means; a fourth voltage pumping capacitor having first and second electrodes, the first electrode be coupled to the output of said input means; a fifth pull-up transistor having its gate connected to the supply voltage and its channel connected between the supply voltage and the second electrode of said fourth voltage pumping capacitor; and a sixth pull-up transistor having its gate connected to the second electrode of said fourth voltage pumping capacitor and its channel connected between the second electrode of said third voltage pumping capacitor and the supply voltage.

Claim 29

The voltage pumping circuit of claim 20, wherein said enable input signal is one of a first signal generated in association with row or column address strobe signals and a second signal generated upon a power-up of the semiconductor memory device.

Claim 30

A voltage pumping circuit having an input node for sensing transition of an enable input signal and compensating for a voltage drop of a pumped voltage output therefrom, comprising: voltage pumping means coupled to said input node for generating said pumped voltage in response to a voltage level transition of the enable input signal; precharge means coupled to said input node for precharging an output of said voltage pumping means to a voltage which is substantially identical to a source supply voltage during non-active operational mode of the semiconductor memory device; output means for outputting the pumped voltage of said voltage pumping means during active operational mode of the semiconductor memory device; and control means for controlling operation of said output means in response to the enable input signal at the input node.

Claim 31

A voltage pumping circuit having an input node for sensing transition of an enable input signal and compensating for a voltage drop of a pumped voltage output therefrom, comprising: voltage pumping means coupled to said input node for generating said pumped voltage in response to a voltage level transition of the enable input signal; precharge means coupled to said input node for precharging an output of said voltage pumping means to a voltage which is substantially identical to a source supply voltage during non-active operational mode of the semiconductor memory device; output means for outputting the pumped voltage of said voltage pumping means during active operational mode of the semiconductor memory device; and control means for controlling operation of said output means in response to the enable input signal at the input node.

Claim 32

The voltage pumping circuit of claim 25, wherein said enable input signal is one of a first signal generated in association with row or column address strobe signals and a second signal generated upon a power-up of the semiconductor memory device.

Claim 33

A semiconductor memory device having electrical circuitry to which is applied a pumped voltage higher than a supply voltage, said semiconductor memory device comprising: a voltage pumping node coupled to the electrical circuitry; voltage pumping means for pumping up the voltage level to be sent to the voltage pumping node during a power-up cycle of the semiconductor memory device to generate the pumped voltage; isolation means for supplying the pumped voltage to said voltage pumping node; active kicker means coupled to the voltage pumping means for compensating for a voltage drop in the pumped voltage in response to signals output from the electrical circuitry; detecting means for feeding-back to said voltage pumping means a sensing signal indicative of a variation in the pumped voltage; and clamping means for receiving the sensing signal to clamp the pumped voltage so as to compensate for a voltage level pulled-up above a predetermined maximum.

Claim 34

A semiconductor memory device having electrical circuitry to which is applied a pumped voltage higher than a supply voltage, said semiconductor memory device comprising: a voltage pumping node coupled to the electrical circuitry; voltage pumping means for pumping up the voltage level to be sent to the voltage pumping node during a power-up cycle of the semiconductor memory device to generate the pumped voltage; isolation means for supplying the pumped voltage to said voltage pumping node; active kicker means coupled to the voltage pumping means for compensating for a voltage drop in the pumped voltage in response to signals output from the electrical circuitry; detecting means for feeding-back to said voltage pumping means a sensing signal indicative of a variation in the pumped voltage; and clamping means for receiving the sensing signal to clamp the pumped voltage so as to compensate for a voltage level pulled-up above a predetermined maximum.

Claim 35

The semiconductor memory device of claim 27, wherein said voltage pumping means comprises: an oscillator for generating a pumping clock in response to the supply voltage and the sensing signal; and first and second charge pumps having first and second pumping nodes, said first and second charge pumps each operating complementarily in response to the pumping clock.

Claim 36

The semiconductor memory device of claim 28, wherein said isolation means comprises: a first isolation transistor having its gate connected to the first pumping node and its channel connected between the first pumping node and the voltage pumping node; and a second isolation transistor having its gate connected to the second pumping node and its channel connected between the second pumping node and the voltage pumping node.

Claim 37

The semiconductor memory device of claim 29, further comprising precharge means for precharging the voltage level at said first and second pumping nodes to a predetermined voltage.

Claim 38

The semiconductor memory device of claim 27, further comprising means for precharging the voltage level at the voltage pumping node to a predetermined voltage.

Claim 39

The semiconductor memory device of claim 27, wherein said active kicker means comprises: a logic combination circuit for receiving signals from the electrical circuitry; a kicking node; a pre-kicker for setting a voltage at the kicking node to a first level when the output of the logic combination circuit is at a first state; a kicking driver for converting the voltage at the kicking node from said first level to a second level when the output of the logic combination circuit is at a second state; and a third isolation transistor having its channel connected between the kicking node and the voltage pumping node.

Claim 40

The semiconductor memory device of claim 27, wherein said clamping means comprises a DC current path controllable by the sensing signal, disposed in series between the pumped voltage and the supply voltage.

Claim 41

The semiconductor memory device of claim 27, wherein said clamping means comprises a DC current path disposed in series between the pumped voltage and the supply voltage.

Claim 42

A semiconductor memory device including: a plurality of memory cells; a plurality of word lines coupled to the memory cells; a plurality of bit line pairs coupled to the memory cells; a plurality of input/output lines coupled to the bit line pairs; a plurality of sense amplifiers coupled to the bit line pairs for amplifying a voltage difference between the respective bit lines in each pair; a plurality of isolation gates coupled between the bit line pairs and the input/output lines; and a plurality of word line drivers for selecting the word lines, said semiconductor memory device further comprising: a voltage pumping node coupled to respective input nodes in said semiconductor memory device to which a pumped voltage is provided; voltage pumping means for generating the pumped voltage at a power-up cycle of the semiconductor memory device; isolation means for supplying the pumped voltage to said voltage pumping node; active kicker means coupled to said voltage pumping means for compensating for a voltage drop in the pumped voltage, said active kicker means receiving a voltage signal from output nodes in said semiconductor memory device to which a pumped voltage has been provided; detecting means for feeding-back to said voltage pumping means a sensing signal indicative of a variation in the pumped voltage; and clamping means for receiving the sensing signal to clamp the pumped voltage so as to compensate for a pulse voltage level pulled-up above a predetermined maximum.

Claim 43

A semiconductor memory device including: a plurality of memory cells; a plurality of word lines coupled to the memory cells; a plurality of bit line pairs coupled to the memory cells; a plurality of input/output lines coupled to the bit line pairs; a plurality of sense amplifiers coupled to the bit line pairs for amplifying a voltage difference between the respective bit lines in each pair; a plurality of isolation gates coupled between the bit line pairs and the input/output lines; and a plurality of word line drivers for selecting the word lines, said semiconductor memory device further comprising: a voltage pumping node coupled to respective input nodes in said semiconductor memory device to which a pumped voltage is provided; voltage pumping means for generating the pumped voltage at a power-up cycle of the semiconductor memory device; isolation means for supplying the pumped voltage to said voltage pumping node; active kicker means coupled to said voltage pumping means for compensating for a voltage drop in the pumped voltage, said active kicker means receiving a voltage signal from output nodes in said semiconductor memory device to which a pumped voltage has been provided; detecting means for feeding-back to said voltage pumping means a sensing signal indicative of a variation in the pumped voltage; and clamping means for receiving the sensing signal to clamp the pumped voltage so as to compensate for a pulse voltage level pulled-up above a predetermined maximum.

Claim 44

The semiconductor memory device of claim 35, wherein said voltage pumping means comprises: an oscillator for generating a pumping clock in response to states of a supply voltage and the sensing signal; and first and second charge pumps having first and second pumping nodes, said first and second charge pumps each operating complementarily in response to the pumping clock.

Claim 45

The semiconductor memory device of claim 36, wherein said isolation means comprises: a first isolation transistor having its gate connected to the first pumping node and its channel connected between the first pumping node and the voltage pumping node; and a second isolation transistor having its gate connected to the second pumping node and its channel connected between the second pumping node and the voltage pumping node.

Claim 46

The semiconductor memory device of claim 37, further comprising means for precharging a voltage at the first and second pumping nodes to a predetermined voltage.

Claim 47

The semiconductor memory device of claim 35, further comprising means for precharging a voltage at the voltage pumping node to a predetermined voltage.

Claim 48

The semiconductor memory device of claim 35, wherein said active kicker means comprises: a logic combination circuit for receiving control signals from the semiconductor memory device output nodes; a kicking node; a pre-kicker for setting a voltage at the kicking node to first level when the output of the logic combination circuit is at a first state; a kicking driver for converting the voltage at the kicking node from said first level to a second level when the output of the logic combination circuit is at a second state; and a third isolation transistor having its channel connected between the kicking node and the voltage pumping node.

Claim 49

The semiconductor memory device of claim 35, wherein said clamping means comprises a DC current path controllable by the sensing signal, disposed in series between the pumped voltage and the supply voltage.

Claim 50

The semiconductor memory device of claim 35, wherein said clamping means comprise a DC current path disposed in series between the pumped voltage and the supply voltage.

Claim 51

The semiconductor memory device of claim 35, wherein said clamping means comprises: a first clamping circuit for supplying a first voltage to the voltage pumping node if the supply voltage is identical to the first voltage; and a second clamping circuit for supplying a second voltage higher than the first voltage to the voltage pumping node if the supply voltage is identical to the second voltage.