US5365547A
Expired / Lapsed
US
⏱️ 0.0 years remaining
1X asynchronous data sampling clock for plus minus topology applications
Assignee: Individual
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Filing: 1992-07-16
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Granted: 1994-11-15
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Expires: 2012-07-16
Abstract
Abstract The present invention relates to a system for asynchronous transmission and reception of data between control units. The system includes a first control unit which is operatively connected to a first asynchronous transmitter-receiver circuit, a second control unit operatively connected to a second asynchronous transmitter-receiver circuit and a single media connected between the first and second control units, which facilitates serial communication of data therebetween. Each asynchronous transmitter receiver circuit includes a transmitter portion having circuit for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz, and a receiver portion for processing received data signals and extracting the odd and even data bits therefrom. The receiver portion has a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of the received data signals, and circuit for determining a true center of the received data signals and for selecting a proper sampling clock for the received data signals. The system also includes an interface portion for serially transmitting the odd and even data bits on a single media in response to the transmitter portion and for receiving serial data from the single media and detecting positive and negative transitions of the received data signals.
Inventors
- 👤 Frank Marinaro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:42
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
182 words
An asynchronous transmitter-receiver circuit for use in local area networks, which comprises: a transmitter portion having means for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz; a receiver portion for processing received data signals and extracting the odd and even data bits therefrom, said receiver portion having a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of said received data signals with respect to a system clock, a bias distortion circuit for determining the pulse width of the received data signals and means for combining and decoding output signals from said received data-to-clock position circuit and said bias distortion circuit to determine a true center of said received data signals and for selecting a proper sampling clock for said received data signals; and an interface portion for serially transmitting said odd and even data bits on a single media in response to said transmitter portion and for receiving serial data from said single media and detecting positive and negative transitions of said received data signals.
Claim 2
Dependent Claim
182 words
An asynchronous transmitter-receiver circuit for use in local area networks, which comprises: a transmitter portion having means for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz; a receiver portion for processing received data signals and extracting the odd and even data bits therefrom, said receiver portion having a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of said received data signals with respect to a system clock, a bias distortion circuit for determining the pulse width of the received data signals and means for combining and decoding output signals from said received data-to-clock position circuit and said bias distortion circuit to determine a true center of said received data signals and for selecting a proper sampling clock for said received data signals; and an interface portion for serially transmitting said odd and even data bits on a single media in response to said transmitter portion and for receiving serial data from said single media and detecting positive and negative transitions of said received data signals.
Claim 3
Dependent Claim
67 words
The transmitter-receiver circuit according to claim 1, wherein said transmitter portion comprises: a pair of shift registers configured so that one of said pair of shift registers processes odd data bits and the other of said pair of shift registers processes even data bits; and oscillator means for clocking said pair of shift registers, said oscillator means having a center frequency between 1 MHz and 40 MHz.
Claim 4
Dependent Claim
19 words
The transmitter-receiver circuit according to claim 2, wherein said oscillator means has a center frequency of b 40 MHz.
Claim 5
Dependent Claim
77 words
The transmitter-receiver circuit according to claim 1, wherein said receiver portion further comprises: a pair of shift registers configured so that one of said pair of shift registers processes odd data bits and the other of said pair of shift registers processes even data bits in response to said data sampling clock circuit; means for latching said processed odd and even data bits; and means for synchronizing said data sampling clock circuit with said received data signals.
Claim 6
Dependent Claim
37 words
The transmitter-receiver circuit according to claim 4, wherein said receiver portion further comprises pulse expansion means for expanding the pulse width of said odd and even data bits prior to processing by said pair of shift registers.
Claim 7
Dependent Claim
39 words
The transmitter-receiver circuit according to claim 1, wherein said interface portion comprises a pulse transformer connected to said transmitter portion, said single media and voltage detecting means for detection said positive and negative transitions of said received data signals.
Claim 8
Dependent Claim
114 words
The transmitter-receiver circuit according to claim 1, wherein said data sampling clock circuit comprises: a multitapped delay line having an input connected to a clock having a center frequency of approximately one-half the frequency of the processing rate for generating a plurality of delays outputs; data latch means for latching at least one of said plurality of delay outputs in response to the detection of said received data signals; a Read only Memory (ROM) for determining said proper sampling clock in response to said latched output of said multitapped delay line; and a multiplexer for selecting said proper sampling clock from said plurality of delay outputs in response to said Read Only Memory (ROM).
Claim 9
Independent Claim
407 words
A system for asynchronous transmission and reception of data between control units, comprising: a first control unit operatively connected to a first asynchronous transmitter-receiver circuit, said first asynchronous transmitter-receiver circuit having a transmitter portion having means for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz; a receiver portion for processing received data signals and extracting the odd and even data bits therefrom, said receiver portion having a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of said received data signals with respect to a system clock, a bias distortion circuit for determining the pulse width of the received data signals and means for combining and decoding output signals from said received data-to-clock position circuit and said bias distortion circuit to determine a true center of said received data signals and for selecting a proper sampling clock for said received data signals; an interface portion for serially transmitting said odd and even data bits on a single media in response to said transmitter portion and for receiving serial data from said single media and detecting positive and negative transitions of said received data signals; a second control unit operatively connected to a second asynchronous transmitter-receiver circuit, said second asynchronous transmitter-receiver circuit having a transmitter portion having means for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz; a receiver portion for processing received data signals and extracting the odd and even data bits therefrom, said receiver portion having a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of said received data signals with respect to a system clock, a bias distortion circuit for determining the pulse width of the received data signals and means for combining and decoding output signals from said received data-to-clock position circuit and said bias distortion circuit to determine a true center of said received data signals and for selecting a proper sampling clock for said received data signals; an interface portion for serially transmitting said odd and even data bits on a single media in response to said transmitter portion and for receiving serial data from said single media and detecting positive and negative transitions of said received data signals; and a further single media connected between said first and second control units, which facilitates serial communication of data therebetween.
Claim 10
Independent Claim
407 words
A system for asynchronous transmission and reception of data between control units, comprising: a first control unit operatively connected to a first asynchronous transmitter-receiver circuit, said first asynchronous transmitter-receiver circuit having a transmitter portion having means for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz; a receiver portion for processing received data signals and extracting the odd and even data bits therefrom, said receiver portion having a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of said received data signals with respect to a system clock, a bias distortion circuit for determining the pulse width of the received data signals and means for combining and decoding output signals from said received data-to-clock position circuit and said bias distortion circuit to determine a true center of said received data signals and for selecting a proper sampling clock for said received data signals; an interface portion for serially transmitting said odd and even data bits on a single media in response to said transmitter portion and for receiving serial data from said single media and detecting positive and negative transitions of said received data signals; a second control unit operatively connected to a second asynchronous transmitter-receiver circuit, said second asynchronous transmitter-receiver circuit having a transmitter portion having means for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz; a receiver portion for processing received data signals and extracting the odd and even data bits therefrom, said receiver portion having a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of said received data signals with respect to a system clock, a bias distortion circuit for determining the pulse width of the received data signals and means for combining and decoding output signals from said received data-to-clock position circuit and said bias distortion circuit to determine a true center of said received data signals and for selecting a proper sampling clock for said received data signals; an interface portion for serially transmitting said odd and even data bits on a single media in response to said transmitter portion and for receiving serial data from said single media and detecting positive and negative transitions of said received data signals; and a further single media connected between said first and second control units, which facilitates serial communication of data therebetween.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |