US5361264A
Expired / Lapsed
US
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Mode programmable VLSI data registers
Assignee: Raytheon Co
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Filing: 1993-02-22
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Granted: 1994-11-01
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Expires: 2013-02-22
Abstract
Abstract Mode programmable VLSI CMOS data registers perform on-chip self-test. A first data register performs storage or transfer of data, operates in a scan mode or generates pseudo-random numbers (PRN). A second data register performs storage or transfer of data, operates in a scan mode or performs signature analysis. Data initialization of the registers occurs automatically when operating in a test mode.
Inventors
- 👤 Edward T. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:42
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/3183; G01R31/318385; G01R31/318555
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
121 words
A mode programmable data register having a plurality of stages comprising: means having a scan input, a parallel data input and a parallel initialization input for storing data; means coupled to said storing means for automatically initializing said mode programmable data register to one of a plurality of predetermined states in accordance with said parallel initialization input to each stage, said initializing being performed during a first clock period of a pseudo-random number generator mode of operation following the assertion of a test enable control signal; means coupled to outputs of predetermined stages of said data register for enabling said register to generate pseudo-random numbers; and means coupled to said storing means for operating said data register in a scan mode.
Claim 2
Dependent Claim
121 words
A mode programmable data register having a plurality of stages comprising: means having a scan input, a parallel data input and a parallel initialization input for storing data; means coupled to said storing means for automatically initializing said mode programmable data register to one of a plurality of predetermined states in accordance with said parallel initialization input to each stage, said initializing being performed during a first clock period of a pseudo-random number generator mode of operation following the assertion of a test enable control signal; means coupled to outputs of predetermined stages of said data register for enabling said register to generate pseudo-random numbers; and means coupled to said storing means for operating said data register in a scan mode.
Claim 3
Dependent Claim
121 words
A mode programmable data register having a plurality of stages comprising: means having a scan input, a parallel data input and a parallel initialization input for storing data; means coupled to said storing means for automatically initializing said mode programmable data register to one of a plurality of predetermined states in accordance with said parallel initialization input to each stage, said initializing being performed during a first clock period of a signature analysis mode of operation following the assertion of a test enable control signal; means coupled to outputs of predetermined stages of said data registers for enabling said register to perform said signature analysis; and means coupled to said storing means for operating said data register in a scan mode.
Claim 4
Dependent Claim
121 words
A mode programmable data register having a plurality of stages comprising: means having a scan input, a parallel data input and a parallel initialization input for storing data; means coupled to said storing means for automatically initializing said mode programmable data register to one of a plurality of predetermined states in accordance with said parallel initialization input to each stage, said initializing being performed during a first clock period of a signature analysis mode of operation following the assertion of a test enable control signal; means coupled to outputs of predetermined stages of said data registers for enabling said register to perform said signature analysis; and means coupled to said storing means for operating said data register in a scan mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |