US5359627A
Expired / Lapsed
US
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Channel codec apparatus and method utilizing flat codes
Assignee: Aware Inc
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Filing: 1993-07-01
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Granted: 1994-10-25
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Expires: 2013-07-01
Abstract
Abstract A channel coding system comprising apparatuses and methods for encoding and decoding signals is disclosed. The system utilizes an orthonormal basis of numerical sequences for coding an input signal. The orthonormal bases reduce channel interference. A method for generating long basis sequences from the product of shorter sequences is also disclosed.
Inventors
- 👤 Howard L. Resnikoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:56
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H04; H04L; H04L23/00; H04L23/02
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
264 words
A signal encoding apparatus comprising: means for receiving an input signal comprising an ordered sequence of symbols; memory means for storing at least a portion of a first channel coding basis comprising one or more flat channel sequences, each said channel sequence comprising an array of numerical values of length L, where L≧2, the number of said channel sequences being less than or equal to μ, wherein μ is equal to the multiplier of said first channel coding basis; clock means for generating a sequence of timing signals; control means for generating a sum array comprising an ordered array of numerical values α(k), for k=0 to (L-1), said control means comprising means for selecting a said channel sequence and for multiplying said selected channel sequence by a numerical value depending on one of said received symbol; means for storing a channel array comprising an ordered array of numerical values β(k) for k=0 to L-1; means for combining said sum array with said channel array comprising means for adding α(k) to β(k+μq), where q is a positive integer, said combining means being responsive to said clock means having generated μq said timing signals; and shifting means for outputting β(L-1), for replacing β(k) by β(k-1) for k=1 to (L-1), and for replacing β(0) by 0, said shifting means being responsive to said clock means having generated one of said timing signal; wherein said control means being operatively connected to said receiving means, said memory means, said clock means, said means for storing a channel array, said means for combining said sum array, and said shifting means.
Claim 2
Dependent Claim
264 words
A signal encoding apparatus comprising: means for receiving an input signal comprising an ordered sequence of symbols; memory means for storing at least a portion of a first channel coding basis comprising one or more flat channel sequences, each said channel sequence comprising an array of numerical values of length L, where L≧2, the number of said channel sequences being less than or equal to μ, wherein μ is equal to the multiplier of said first channel coding basis; clock means for generating a sequence of timing signals; control means for generating a sum array comprising an ordered array of numerical values α(k), for k=0 to (L-1), said control means comprising means for selecting a said channel sequence and for multiplying said selected channel sequence by a numerical value depending on one of said received symbol; means for storing a channel array comprising an ordered array of numerical values β(k) for k=0 to L-1; means for combining said sum array with said channel array comprising means for adding α(k) to β(k+μq), where q is a positive integer, said combining means being responsive to said clock means having generated μq said timing signals; and shifting means for outputting β(L-1), for replacing β(k) by β(k-1) for k=1 to (L-1), and for replacing β(0) by 0, said shifting means being responsive to said clock means having generated one of said timing signal; wherein said control means being operatively connected to said receiving means, said memory means, said clock means, said means for storing a channel array, said means for combining said sum array, and said shifting means.
Claim 3
Dependent Claim
26 words
The signal encoding apparatus of claim 1 wherein said channel sequence selected by said control means depends on the order of receipt of said received symbol.
Claim 4
Dependent Claim
42 words
The signal encoding apparatus of claim 1 wherein said means for multiplying said selected channel sequence by a numerical value in said control means comprises means for multiplying said channel sequence by a numerical value depending on one of said received symbol.
Claim 5
Dependent Claim
206 words
A signal decoding apparatus comprising: means for receiving an input signal; clock means for generating a sequence of timing signals; means for generating an ordered sequence of numerical values from said input signal and for storing the previously received L said numerical values, where L ≧2, said generating means being responsive to said timing signals; memory means for storing at least a portion of a first channel coding basis comprising one or more channel sequences, each said channel sequence comprising an array of numerical values of length L, each said numerical value having one of two possible values, the number of said channel sequences being less than or equal to μ, wherein μ is equal to the multiplier of said channel coding basis; correlation means, operatively connected to said receiving means, said clock means, said means for generating an ordered sequence, and said memory means, for generating a signal related to the cross-correlation of said stored L and one of said channel sequence stored in said memory means, said correlation means being responsive to said clock means having generated qμ said timing signals wherein q is a predetermined positive integer; and means for outputting a value related to said generated signal generated by said correlation means.
Claim 6
Dependent Claim
206 words
A signal decoding apparatus comprising: means for receiving an input signal; clock means for generating a sequence of timing signals; means for generating an ordered sequence of numerical values from said input signal and for storing the previously received L said numerical values, where L ≧2, said generating means being responsive to said timing signals; memory means for storing at least a portion of a first channel coding basis comprising one or more channel sequences, each said channel sequence comprising an array of numerical values of length L, each said numerical value having one of two possible values, the number of said channel sequences being less than or equal to μ, wherein μ is equal to the multiplier of said channel coding basis; correlation means, operatively connected to said receiving means, said clock means, said means for generating an ordered sequence, and said memory means, for generating a signal related to the cross-correlation of said stored L and one of said channel sequence stored in said memory means, said correlation means being responsive to said clock means having generated qμ said timing signals wherein q is a predetermined positive integer; and means for outputting a value related to said generated signal generated by said correlation means.
Claim 7
Dependent Claim
42 words
The signal decoding apparatus of claim 4 further comprising delay means for between said receiving means and said generating means for introducing a variable delay between the receipt of said input signal and the generation of said ordered sequence of numerical values.
Claim 8
Independent Claim
197 words
A method for encoding a signal comprising the steps: receiving an input signal comprising an ordered sequence of symbols; storing at least a portion of a first channel coding basis comprising one or more channel sequences, each said channel sequence comprising an array of numerical values of length L, each said numerical value having one of two possible values, the number of said channel sequences being less than or equal to μ, wherein μ is equal to the multiplier of said first channel coding basis; generating a sequence of timing signals; generating a sum array comprising an ordered array of numerical values α(k), for k=0 to (L-1), said generating step comprises selecting a said channel sequence and multiplying said selected channel sequence by a numerical value; storing a channel array comprising an ordered array of numerical values β(k) for k=0 to L-1; combining said sum array with said channel array, said combining step comprising adding α(k) to β(k+μq), where q is a positive integer, said combining step being responsive to the generation of μq said timing signals; and at each timing signal, outputting β(L-1), replacing β(k) by β(k-1) for k=1 to (L-1), and replacing β(0) by 0.
Claim 9
Independent Claim
197 words
A method for encoding a signal comprising the steps: receiving an input signal comprising an ordered sequence of symbols; storing at least a portion of a first channel coding basis comprising one or more channel sequences, each said channel sequence comprising an array of numerical values of length L, each said numerical value having one of two possible values, the number of said channel sequences being less than or equal to μ, wherein μ is equal to the multiplier of said first channel coding basis; generating a sequence of timing signals; generating a sum array comprising an ordered array of numerical values α(k), for k=0 to (L-1), said generating step comprises selecting a said channel sequence and multiplying said selected channel sequence by a numerical value; storing a channel array comprising an ordered array of numerical values β(k) for k=0 to L-1; combining said sum array with said channel array, said combining step comprising adding α(k) to β(k+μq), where q is a positive integer, said combining step being responsive to the generation of μq said timing signals; and at each timing signal, outputting β(L-1), replacing β(k) by β(k-1) for k=1 to (L-1), and replacing β(0) by 0.
Claim 10
Dependent Claim
19 words
The method of claim 6 wherein said selected channel depends on the order of receipt of said received symbol.
Claim 11
Dependent Claim
34 words
The method of claim 6 wherein said step of multiplying said selected channel sequence by a numerical value comprises multiplying said channel sequence by a numerical value depending on one of said received symbol.
References Cited (Backward Citations)
US5081645A
Cited
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| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
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