Row interleaved frame buffer

Claim 2

An improved frame buffer in a computer system having a display means, said display means having multiple display lines, said improved frame buffer comprising: a) multiple banks of display memory wherein each said display memory bank provides display data for a different non-contiguous set of said display lines of said display means; and, b) separate display memory access logic for each said display memory bank, wherein said separate display memory logic comprises: i) means for decoding, in response to receiving a read or write command, a provided memory address and to provide a decoded row address and a decoded column address to one of said display memory banks; and ii) means for determining whether said decoded row address matches a previous decoded row address and accessing said display memory bank associated with said separate display memory access logic if said decoded row address matches said previous decoded row address.

Claim 3

The improved frame buffer of claim 1 wherein an Nth line of said non-contiguous display lines of said display means is driven by a memory bank M of said display memory banks, wherein M=(N modulo a total number of said display memory banks).

Claim 4

The improved frame buffer of claim 2 wherein there are four said display memory banks.

Claim 5

The improved frame buffer of claim 3 wherein each said display memory bank comprises 512K bytes.

Claim 6

The improved frame buffer of claim 4 wherein there are 480 said display lines of said display means.

Claim 7

The improved frame buffer of claim 5 wherein said display means comprises 640 display columns.

Claim 8

An improved frame buffer in a computer system having a display means, said display means having an X number of display rows, said improved frame buffer comprising a Y number of banks of display memory, wherein said improved frame buffer comprises: i) means for decoding, in response to receiving a read or write command, a provided memory address and to provide a decoded row address and a decoded column address to one of said display memory banks; ii) means for determining whether said decoded row address matches a previous decoded row address; and, iii) means for accessing a memory bank Z of said Y banks of display memory, wherein Z=(N modulo Y), if said decoded row address matches said previous decoded row address, and also when said computer system accesses said display memory associated With an Nth row of said X display rows of said display means.

Claim 9

An improved frame buffer in a computer system having a display means, said display means having an X number of display rows, said improved frame buffer comprising a Y number of banks of display memory, wherein said improved frame buffer comprises: i) means for decoding, in response to receiving a read or write command, a provided memory address and to provide a decoded row address and a decoded column address to one of said display memory banks; ii) means for determining whether said decoded row address matches a previous decoded row address; and, iii) means for accessing a memory bank Z of said Y banks of display memory, wherein Z=(N modulo Y), if said decoded row address matches said previous decoded row address, and also when said computer system accesses said display memory associated With an Nth row of said X display rows of said display means.

Claim 10

An improved frame buffer access method in a computer system, said computer system comprising a processor, X banks of display memory means and a display means having Y display rows, said improved frame buffer access method comprising: a) decoding, in response to receiving a read or write command, a provided memory address to provide a decoded row address and a decoded column address to one of said display memory banks; b) determining whether said decoded row address matches a previous decoded row address; and c) if said decoded row address match said previous decoded row address, accessing a set of data corresponding to an Nth display row of said display means by accessing bank M of said X banks of display memory means, wherein M=(N modulo X).

Claim 11

An improved frame buffer access method in a computer system, said computer system comprising a processor, X banks of display memory means and a display means having Y display rows, said improved frame buffer access method comprising: a) decoding, in response to receiving a read or write command, a provided memory address to provide a decoded row address and a decoded column address to one of said display memory banks; b) determining whether said decoded row address matches a previous decoded row address; and c) if said decoded row address match said previous decoded row address, accessing a set of data corresponding to an Nth display row of said display means by accessing bank M of said X banks of display memory means, wherein M=(N modulo X).

Claim 12

A frame buffer access method in a computer system, the computer system having a display means, said display means having a plurality of display rows, and a plurality of memory means, with Y being the total number of said memory means in said computer system, said frame buffer access method comprising: providing a plurality of memory banks; decoding in response to receiving a read or write command a provided memory address, and generating a decoded row address signal and a decoded column address signal; detecting whether said row address matches a previously decoded row address, wherein if a matching row address is detected, then providing said decoded column address to memory bank Z of said plurality of memory banks, wherein Z=(N modulo Y) with N corresponding to a current row number of said display means being accessed, and: wherein if a matching row address is not detected, then providing said decoded row address to said memory bank Z.

Claim 13

A frame buffer access method in a computer system, the computer system having a display means, said display means having a plurality of display rows, and a plurality of memory means, with Y being the total number of said memory means in said computer system, said frame buffer access method comprising: providing a plurality of memory banks; decoding in response to receiving a read or write command a provided memory address, and generating a decoded row address signal and a decoded column address signal; detecting whether said row address matches a previously decoded row address, wherein if a matching row address is detected, then providing said decoded column address to memory bank Z of said plurality of memory banks, wherein Z=(N modulo Y) with N corresponding to a current row number of said display means being accessed, and: wherein if a matching row address is not detected, then providing said decoded row address to said memory bank Z.