Row redundancy circuit of a semiconductor memory device

Claim 1

A semiconductor memory device disposed on a semiconductor chip comprising: a plurality of memory cell arrays arranged in rows and columns, each memory cell array containing a plurality of memory cells for storing data and normally addressable using a normal row address and a normal column address; a normal row decoder associated with each of said plurality of memory cell arrays for decoding said normal row address to obtain a decoded normal row address signal corresponding to one of said rows; means for selecting one of said rows in said memory array using said decoded normal row address signal, said means for selecting including a plurality of word lines; a plurality of sense amplifier arrays, each sense amplifier array connected to one of said plurality of memory cell arrays, for sensing said data stored in said memory cells; a redundant memory cell array disposed within one of said plurality of memory cell arrays for storing data in a plurality of redundant memory cells, said redundant memory array connected to one of said sense amplifier arrays; a plurality of redundant row address decoders, each redundant row address decoder programmed to decode a redundant row address corresponding to a defective normal memory cell address and which outputs a redundant decoded row address signal when said redundant row address is decoded; redundant means for selecting at least one of said rows in said redundant memory array using at least one of said decoded redundant row address signals, said redundant means for selecting including a plurality of redundant word lines; and a control circuit for inputting each of said redundant decoded row address signals and outputting a redundancy control signal to each of said normal row decoders and each of said sense amplifier arrays.