US5355337A
Expired / Lapsed
US
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Arrangement of redundant cell array for semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-04-13
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Granted: 1994-10-11
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Expires: 2012-04-13
Abstract
Abstract In a semiconductor memory device having a normal memory cell array which includes repeating arrangements of a predetermined data arrangement and whose data is input and output in response to a column select line signal, an arrangement of a redundant cell array is disclosed. The arrangement has the same data arrangement as the minimally repeated unit of said normal memory cell array, wherein the data is in the redundant cell array input and output in response to a redundant column select line signal. According to the arrangement of the redundant cell array, the reliability and yield of the semiconductor memory device are enhanced.
Inventors
- 👤 Tae-Jin Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:40
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
171 words
A semiconductor device comprising: a first number of redundant memory cell arrays and a second number of normal memory cell arrays, said first number being less than said second number, each of said redundant and normal memory cell arrays comprising: a plurality of repeat arrangements of a predetermined unit, said predetermined unit comprising a first and second bit line group, each bit line group being controllable for inputting and outputting data by a first and a second column select signal; said first bit line group having bit lines arranged in a first logic arrangement defined as (0101) and said second bit line group having bit lines arranged in a second successive logic arrangement defined as (1010); wherein each redundant memory cell array is built up by repeating an arrangement of a smallest length unit of a corresponding normal cell array, said smallest length unit comprising a first and second redundant bit line group for inputting and outputting data by one of a corresponding first and second redundant column select line signals.
Claim 2
Dependent Claim
171 words
A semiconductor device comprising: a first number of redundant memory cell arrays and a second number of normal memory cell arrays, said first number being less than said second number, each of said redundant and normal memory cell arrays comprising: a plurality of repeat arrangements of a predetermined unit, said predetermined unit comprising a first and second bit line group, each bit line group being controllable for inputting and outputting data by a first and a second column select signal; said first bit line group having bit lines arranged in a first logic arrangement defined as (0101) and said second bit line group having bit lines arranged in a second successive logic arrangement defined as (1010); wherein each redundant memory cell array is built up by repeating an arrangement of a smallest length unit of a corresponding normal cell array, said smallest length unit comprising a first and second redundant bit line group for inputting and outputting data by one of a corresponding first and second redundant column select line signals.
Claim 3
Dependent Claim
86 words
The semiconductor device of claim 1, wherein said first and second redundant column select line signals is output from a logic decoder circuit coupled to said redundant memory cell arrays, said logic decoder circuit being responsive to an external signal, indicative of a faulty cell in one of said normal memory cell arrays, and to a bit-addressing signal, for selectively controlling a logical replacement of said faulty memory cell with a redundant memory cell in a corresponding redundant memory cell array having a similar repeat arrangement.
Claim 4
Dependent Claim
82 words
The semiconductor device of claim 1, wherein said first and second redundant column select line signals is output from a programmable fuse circuit coupled to said redundant memory cell arrays, said programmable fuse circuit being responsive to a programmed fusing signal, indicative of a faulty cell in one of said normal memory cell arrays, for selectively controlling a logical replacement of said faulty memory cell with a redundant memory cell in a corresponding redundant memory cell array having a similar repeat arrangement.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |