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US5355164A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus of correction image read signals by removing the influence of dark current therefrom

Assignee: Fujifilm Holdings Corp
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Filing: 1992-06-23
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Granted: 1994-10-11
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Expires: 2012-06-23
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Abstract

Abstract A method of correcting image read signals including the steps of reading an image line by line by a linear sensor; determining an average value when a plurality of lines of a plurality of blind pixels of the linear sensor are read, computing the signals read from the image by using the average value so as to correct an influence of a dark current of said linear sensor, and outputting said computed signal as the image read signal. According to the present invention, the dark current can be accurately obtained according to the read state without being affected by errors in measurement due to the variations in each of the one-line pixels or due to noise.

Inventors

  • 👤 Yuji Shimoyama
  • 👤 Yoko Takada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 11:44
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/701; H04N25/60; H04N25/63; H04N25/67; H04N25/671; H04N25/673

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 235 words
An apparatus for correcting image read signals comprising: a linear sensor for reading an image line by line and outputting read pixel signals of said image and blind pixel signals; an A/D converter for converting an output signal of said linear sensor into a digital signal; a shift register, coupled to an output of said A/D converter for receiving said digital signal, for storing and outputting a plurality of blind pixel signals of a plurality of lines; line memories, coupled to said output of said A/D converter for storing said digital signal; a first subtracter for subtracting blind pixel signals from a plurality of preceding lines from blind pixel signals of a current line; an adder, having a first input coupled to an output of said first subtracter and a second input for outputting addition data; a first latch circuit for latching the addition data from the adder, and having an output coupled to said second input of the adder; a second latch circuit for storing the addition data; a divider for dividing an output of said second latch circuit so as to obtain an average value; a second subtracter for subtracting the average value from an output of at least one of said line memories, and for outputting a corrected signal; and a timing generating circuit for controlling said line memories, said shift register and said first and second latch circuits by timing signals.
Claim 2
Independent Claim 235 words
An apparatus for correcting image read signals comprising: a linear sensor for reading an image line by line and outputting read pixel signals of said image and blind pixel signals; an A/D converter for converting an output signal of said linear sensor into a digital signal; a shift register, coupled to an output of said A/D converter for receiving said digital signal, for storing and outputting a plurality of blind pixel signals of a plurality of lines; line memories, coupled to said output of said A/D converter for storing said digital signal; a first subtracter for subtracting blind pixel signals from a plurality of preceding lines from blind pixel signals of a current line; an adder, having a first input coupled to an output of said first subtracter and a second input for outputting addition data; a first latch circuit for latching the addition data from the adder, and having an output coupled to said second input of the adder; a second latch circuit for storing the addition data; a divider for dividing an output of said second latch circuit so as to obtain an average value; a second subtracter for subtracting the average value from an output of at least one of said line memories, and for outputting a corrected signal; and a timing generating circuit for controlling said line memories, said shift register and said first and second latch circuits by timing signals.
Claim 3
Dependent Claim 30 words
An apparatus as claimed in claim 1, wherein said digital signal is 4 bits, the number of said line memories is three and a divisor of said divider is 40.
Claim 4
Independent Claim 231 words
An apparatus for correcting image read signals comprising: a linear sensor for reading an image line by line and outputting read pixel signals of said image and blind pixel signals; an A/D converter for converting an output signal of said linear sensor into a digital signal; a shift register, coupled to an output of said A/D converter for receiving said digital signal, for storing and outputting a plurality of blind pixel signals of a plurality of lines; line memories, coupled to said output of said A/D converter, for storing said digital signal; a first subtracter for subtracting blind pixel signals from a plurality of preceding lines from blind pixels from a current line; an adder having a first input coupled to an output of said first subtracter and a second input for outputting addition data; a first latch circuit for latching the addition data from the adder, and having an output coupled to said second input of the adder; a second latch circuit for storing the addition data and for obtaining an average value by outputting a portion of said stored addition data; a second subtracter for subtracting the average value from the output of at least one of said line memories, and for outputting a corrected signal; and a timing generating circuit for controlling said line memories, said shift register and said first and second latch circuits by timing signals.
Claim 5
Independent Claim 231 words
An apparatus for correcting image read signals comprising: a linear sensor for reading an image line by line and outputting read pixel signals of said image and blind pixel signals; an A/D converter for converting an output signal of said linear sensor into a digital signal; a shift register, coupled to an output of said A/D converter for receiving said digital signal, for storing and outputting a plurality of blind pixel signals of a plurality of lines; line memories, coupled to said output of said A/D converter, for storing said digital signal; a first subtracter for subtracting blind pixel signals from a plurality of preceding lines from blind pixels from a current line; an adder having a first input coupled to an output of said first subtracter and a second input for outputting addition data; a first latch circuit for latching the addition data from the adder, and having an output coupled to said second input of the adder; a second latch circuit for storing the addition data and for obtaining an average value by outputting a portion of said stored addition data; a second subtracter for subtracting the average value from the output of at least one of said line memories, and for outputting a corrected signal; and a timing generating circuit for controlling said line memories, said shift register and said first and second latch circuits by timing signals.
Claim 6
Dependent Claim 23 words
An apparatus as claimed in claim 3, wherein said digital signal is 4 bits and the number of said line memories is eight.

References Cited (Backward Citations)

JPS53123617A Cited
US4293877A Cited
US4558366A Cited
JPS60180377A Cited
JPH02179069A Cited
US5132801A Cited
US5153421A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-10-10 1998-04-11 1998-10-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-10-10 2002-04-11 2002-10-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-10-10 2006-04-11 2006-10-11 $7700.00 Window Closed / Lapsed

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