Broadband microwave integrated circuit amplifier with capacitive neutralization

Claim 2

A broadband power amplifier for signals having a frequency up to and into the gigahertz range and higher, comprising: a wafer of semiconductor material having an insulating layer spaced from a top surface with an active layer of semiconductor material between said insulating layer and said top surface; first and second amplifier devices formed in said active silicon layer, each of said amplifier devices having parasitic capacitance; first and second inputs; first and second outputs; means connecting said first and second amplifier devices in push-pull circuit configuration between said first and second inputs and said first and second outputs; and a first neutralization capacitor connected between said first input and said second output, and a second neutralization capacitor connected between said second input and said first output, with each of said first and second neutralizing capacitors having a capacitance approximating the parasitic capacitance of one of said amplifier devices.

Claim 3

The amplifier of claim 1 wherein said semiconductor material is a silicon wafer having resistivity of at least 1000 ohm-centimeters and each of said amplifier devices comprises a pair of complimentary MOSFETs formed in the active layer of said silicon wafer.

Claim 4

The amplifier of claim 2 including a positive voltage source and a negative voltage source and wherein each pair of complimentary MOSFETs comprises a P-channel MOSFET and an N-MOSFET each having a gate electrode, a drain electrode and a source electrode, and wherein said means connecting said two pair of complimentary MOSFETs in push-pull circuit configuration comprise means connecting the gate electrodes of the P-channel and N-channel MOSFETs of the first pair of complimentary MOSFETs to said first input and the drain electrodes thereof to the first output, means connecting the gate electrodes of the P-channel and N-channel MOSFETs of the first set of complimentary MOSFETs to said first input, and the drain electrode thereof to the first output, means connecting the gate electrode of the P-channel and N-channel MOSFETs of the second pair of complimentary MOSFETs to the second input, and the drain electrodes thereof to the second output, means connecting the source electrodes of the P-channel MOSFETs of said first and second pairs of complimentary electrodes together and to said positive voltage source, and means connecting the source electrodes of the N-channel MOSFETs of the first and second pairs of complimentary MOSFETs together and to said negative voltage source.

Claim 5

The amplifier of claim 3 wherein each of said MOSFETs comprises a plurality of cells with each cell having a source region, a gate region, and a drain region with each region extending from a top surface of said silicon wafer through said active layer to said insulating layer, said silicon wafer having grooves extending from a bottom surface to said source regions and lined with vias in contact with said source regions, said vias being connected along said bottom surface by a floating ground plane, said amplifier further including gate electrodes associated with the gate region of each cell and connected by a gate bus, and drain conductors connecting said drain regions of each cell.

Claim 6

The amplifier of claim 4 wherein said drain conductors include air bridges extending over, but spaced from, said gate electrodes and the vias contacting the source regions.

Claim 7

The amplifier of claim 4 wherein said means connecting the source electrodes of said MOSFETs comprise microstrips on the upper surface of said wafer, said amplifier further including additional grooves extending from said bottom surface to the top surface and additional vias lining said additional grooves and electrically connecting the floating ground plane for a MOSFET to an associated one of the microstrips on said upper surface of said silicon wafer.