Active power line conditioner with synchronous transformation control

Claim 2

An active power line conditioner comprising: a series inverter coupled to an energy input source; a parallel inverter coupled to a load, said load being powered by a three phase load current which includes fundamental components and harmonic components; an energy storage element electrically connected between said series inverter and said parallel inverter; series filter controller means, coupled to said series inverter, for generating a series filter feedforward signal corresponding to said fundamental component of said load current, said series filter controller means utilizing a synchronous transformation mechanism for processing said load current to generate said series filter feedforward signal; and parallel filter controller means, coupled to said parallel inverter, for producing a parallel filter signal corresponding to said harmonic ripple components of said load current, said parallel filter controller means utilizing a synchronous transformation mechanism for processing output voltages from said load to generate said parallel filter signal; wherein said series filter feedforward signal is applied to said series inverter to generate sinusoidal input currents for said load, and said parallel filter signal is applied to said parallel inverter to generate sinusoidal voltages for said load.

Claim 3

The apparatus of claim 1 wherein said synchronous transformation mechanism includes a 3-to-2 phase transformer which receives said three phase load current and resolves it into a single current vector which rotates at a current vector constant frequency with respect to a stationary reference frame with an i ds axis and an i qs axis; a stationary-to-rotating transformer which receives said current vector and generates a reference frame with an i d axis and an i q axis which rotates at said current vector constant frequency, said stationary-to-rotating transformer converting said current vector into I d and I q signals, each of which includes a dc component, corresponding to said fundamental components of said load current, and superimposed ac components, corresponding to said load current harmonics; and a low pass filter for filtering said superimposed ac components of said I d and I q signals to generate I df and I qf signals corresponding to said fundamental components of said load current.

Claim 4

The apparatus of claim 2 further comprising a rotating-to-stationary transformer to perform the inverse operation of said stationary-to-rotating transformer on said I df and I qf signals to generate I ds ' and I qs ' signals; and a 2-to-3 phase transformer to perform the inverse operation of said 3-to-2 phase transformer on said I ds ' and I qs ' signals, thereby generating a three phase fundamental reference signal corresponding to said fundamental components of said load current.

Claim 5

The apparatus of claim 3 further comprising means for adding a link restoration signal to said three phase fundamental reference signal, said link restoration signal providing a sinusoidal current reference to compensate for energy depleted from said energy storage element.

Claim 6

The apparatus of claim 3 wherein said three phase fundamental reference signal is applied to a series current processor where a series input current is subtracted from said three phase fundamental reference signal to generate a series filter error signal.

Claim 7

The apparatus of claim 5 wherein said series filter error signal is applied to a pulse-width modulator which generates drive signals for said series filter inverter.

Claim 8

The apparatus of claim 2 further comprising means for adding a fundamental regulating current to said I df and I qf signals.

Claim 9

The apparatus of claim 1 further including an energy storage controller for generating a link restoration signal, said energy storage controller multiplying a voltage error signal by instantaneous output voltage reference signals.

Claim 10

The apparatus of claim 8 wherein said voltage error signal is generated by subtracting an energy storage element voltage from an energy storage element reference voltage.

Claim 11

The apparatus of claim 8 wherein said instantaneous output voltage reference signals are established by a rotating-to-stationary transformer and a 2-to-3 phase transformer which operate on first and second output voltage reference signals.

Claim 12

The apparatus of claim 1 wherein said synchronous transformation mechanism includes a 3-to-2 phase transformer which receives a three phase output voltage from said non-linear load and resolves it into a single voltage vector which rotates at a voltage vector constant frequency with respect to a stationary reference frame with a v ds axis and a v qs axis; and a stationary-to-rotating transformer which receives said voltage vector and generates a reference frame with a v d axis and a v q axis which rotates at said voltage vector constant frequency, said stationary-to-rotating transformer converting said voltage vector into v d and v q signals, each of which includes a dc component, corresponding to said fundamental components of said load voltage, and a superimposed ac component, corresponding to load harmonics present in said output voltage.

Claim 13

The apparatus of claim 11 further comprising a rotating-to-stationary transformer to perform the inverse operation of said stationary-to-rotating transformer on said v d and v q signals to generate V ds ' and V qs ' signals; and a 2-to-3 phase transformer to perform the inverse operation of said 3-to-2 phase transformer on said v d and v q signals, thereby generating a three phase fundamental parallel reference signal corresponding to said fundamental components of said load current.

Claim 14

The apparatus of claim 12 further comprising a first mixer for adding said three phase fundamental parallel reference signal with feedback signals corresponding to said load current.

Claim 15

The apparatus of claim 13 further comprising a second mixer for adding said three phase fundamental parallel reference signal with a link restoration signal which compensates for energy depleted from said energy storage element.

Claim 16

The apparatus of claim 14 further comprising a third mixer for adding said three phase fundamental parallel reference signal with the inverse of a parallel inverter feedback signal to generate a parallel filter error signal.

Claim 17

The apparatus of claim 15 wherein said parallel filter error signal is applied to a pulse-width modulator which generates drive signals for said parallel filter inverter.

Claim 18

The apparatus of claim 1 wherein said synchronous transformation mechanism includes a 3-to-2 phase transformer which receives said three phase load current and resolves it into a single current vector which rotates at a current vector constant frequency with respect to a stationary reference frame with an i ds axis and an i qs axis; a stationary-to-rotating transformer which receives said current vector and generates a reference frame with an i d axis and an i q axis which rotates at said current vector constant frequency, said stationary-to-rotating transformer converting said current vector into I d and I q signals, each of which includes a dc component, corresponding to said fundamental components of said load current, and a superimposed ac component, corresponding to said load current harmonics; and a low pass filter for filtering said superimposed ac components of said I d and I q signals to generate I df and I qf signals corresponding to said fundamental components of said load current.

Claim 19

The apparatus of claim 17 further comprising a rotating-to-stationary transformer to perform the inverse operation of said stationary-to-rotating transformer on said I df and I qf signals to generate I df-s and I qf-s signals; and a 2-to-3 phase transformer to perform the inverse operation of said 3-to-2 phase transformer on said I df-s and I qf-s signals, thereby generating a three phase fundamental reference signal corresponding to said fundamental components of said load current.

Claim 20

The apparatus of claim 18 further comprising a mixer for subtracting said three phase fundamental reference signal from instantaneous load current signals to generate a load harmonic error signal.

Claim 21

The apparatus of claim 19 wherein said load harmonic error signal is applied to a pulse-width modulator which generates drive signals for said parallel filter inverter.

Claim 22

The apparatus of claim 1 further including a vector phase-locked loop comprising: a 3-to-2 phase transformer for continuously producing an instantaneous vector sum for first and second serial inverter input voltage signals; a phase detector, coupled to said 3-to-2 phase transformer, for sequentially establishing, from said first and second serial inverter input voltage signals, a plurality of relative phase values Θ between said voltage signals; a timing mechanism for selecting one of said relative phase values Θ to form a selected phase value; and means for defining a sin Θ and a cos Θ value corresponding to said selected phase value.

Claim 23

The apparatus of claim 1 wherein said parallel filter controller means generates an intermediate parallel filter signal corresponding to said fundamental components of said load current, said intermediate parallel filter signal being subtracted from an instantaneous fundamental load current signal to generate said parallel filter signal corresponding to said harmonic ripple components of said load current.

Claim 24

A power filter circuit comprising: a phase-locked loop for establishing first and second relative phase error signals for two voltage reference signals; a parallel inverter coupled to a load, said load being powered by a single phase load current which includes a fundamental component and harmonic components; a parallel filter controller, coupled to said parallel inverter and said phase-locked loop, said parallel filter controller including: means for multiplying said first and second relative phase error signals with said load current to generate a real current signal and a reactive current signal, said real and reactive current signals each including a dc component and an ac component; first and second low pass filters, coupled to said multiplying means, for respectively filtering said real and reactive current signals to yield first and second dc signals corresponding to said dc components of said real and reactive current signals; first and second multipliers for multiplying said first and second dc signals with said load current signals to respectively produce an instantaneous fundamental load active current signal and an instantaneous load reactive current signal; an adder for adding said instantaneous fundamental load active current signal with said instantaneous load reactive current to generate an instantaneous fundamental load current; a subtractor for subtracting said instantaneous fundamental load current from said load current to generate a load harmonic ripple component signal; wherein said load harmonic ripple component signal is applied to said parallel filter to generate sinusoidal voltages for said load.

Claim 25

A power filter circuit comprising: a phase-locked loop for establishing first and second relative phase error signals for two voltage reference signals; a parallel inverter coupled to a load, said load being powered by a single phase load current which includes a fundamental component and harmonic components; a parallel filter controller, coupled to said parallel inverter and said phase-locked loop, said parallel filter controller including: means for multiplying said first and second relative phase error signals with said load current to generate a real current signal and a reactive current signal, said real and reactive current signals each including a dc component and an ac component; first and second low pass filters, coupled to said multiplying means, for respectively filtering said real and reactive current signals to yield first and second dc signals corresponding to said dc components of said real and reactive current signals; first and second multipliers for multiplying said first and second dc signals with said load current signals to respectively produce an instantaneous fundamental load active current signal and an instantaneous load reactive current signal; an adder for adding said instantaneous fundamental load active current signal with said instantaneous load reactive current to generate an instantaneous fundamental load current; a subtractor for subtracting said instantaneous fundamental load current from said load current to generate a load harmonic ripple component signal; wherein said load harmonic ripple component signal is applied to said parallel filter to generate sinusoidal voltages for said load.

Claim 26

The apparatus of claim 23 wherein said phase-locked loop includes: a 3-to-2 phase transformer for continuously producing an instantaneous vector sum for said voltage reference signals; a phase detector, coupled to said 3to-2 phase transformer, for sequentially establishing, from said voltage reference signals, a plurality of relative phase values Θ between said voltage reference signals; a timing mechanism for selecting one of said relative phase values Θ to form a selected phase value; means for defining a sin Θ and a cos Θ value corresponding to said selected phase value, said sin Θ value corresponding to said first relative phase error signal and said cos Θ value corresponding to said second relative phase error signal.

Claim 29

The method of claim 25 further comprising the step of: generating a link restoration signal by multiplying a voltage error signal by instantaneous output voltage reference signals.

Claim 30

The method of claim 26 wherein said voltage error signal is generated by subtracting an energy storage element voltage from an energy storage element reference voltage.

Claim 31

The method of claim 25 wherein said generating step includes the steps of: resolving said three phase load current into a single current vector which rotates at a current vector constant frequency with respect to a stationary reference frame with an i ds axis and an i qs axis; generating from said current vector a reference frame with an i d axis and an i q axis which rotates at said current vector constant frequency, said stationary-to-rotating transformer converting said current vector into I d and I q signals, each of which includes a dc component, corresponding to said fundamental components of said load current, and superimposed ac components, corresponding to said load current harmonics; and low pass filtering said superimposed ac components of said I d and I q signals to generate I df and I qf signals corresponding to said fundamental components of said load current.

Claim 32

The method of claim 28 further comprising the steps of performing the inverse operation of said resolving step on said I df and I qf signals to generate I ds ' and I qs ' signals; and executing the inverse operation of said generating step on said I ds ' and I qs ' signals, thereby generating a three phase fundamental reference signal corresponding to said fundamental components of said load current.

Claim 33

The method of claim 29 further including the step of applying said three phase fundamental reference signal to a series current processor where a series input current is subtracted from said three phase fundamental reference signal to generate a series filter error signal.

Claim 34

The method of claim 30 further comprising the step of applying said series filter error signal to a pulse-width modulator which generates drive signals for said series filter inverter.

Claim 35

The method of claim 31 further comprising the step of adding a fundamental regulating current to said I df and I qf signals.

Claim 36

The method of claim 32 further comprising the step of adding a link restoration signal to said three phase fundamental reference signal, said link restoration signal providing a sinusoidal current reference to compensate for energy depleted from said energy storage link.

Claim 37

The method of claim 25 wherein said producing step includes the steps of: receiving a three phase output voltage from said load and resolving it into a single voltage vector which rotates at a voltage vector constant frequency with respect to a stationary reference frame with a V ds axis and a V qs axis; and generating a reference frame with a V d axis and a V q axis which rotates at said voltage vector constant frequency, said generating step converting said voltage vector into V d and V q signals, each of which includes a dc component corresponding to said fundamental components of said load voltage, and a superimposed ac component, corresponding to load harmonics present in said output voltage.

Claim 38

The method of claim 34 further comprising the steps of: performing the inverse operation of said receiving step on said V d and V q signals to generate V ds and V qs signals; and executing the inverse operation of said generating step on said V d and V q signals, thereby generating a three phase fundamental parallel reference signal corresponding to said fundamental components of said load current.

Claim 39

The method of claim 35 further comprising the step of: adding said three phase fundamental parallel reference signal to feedback signals corresponding to said load current.

Claim 40

The method of claim 36 further comprising the step of: adding said three phase fundamental parallel reference signal to a link restoration signal which compensates for energy depleted from said energy storage element.

Claim 41

The method of claim 37 further comprising the step of: adding said three phase fundamental parallel reference signal to the inverse of a parallel inverter feedback signal to generate a parallel filter error signal.

Claim 42

The method of claim 38 further comprising the step of: applying said parallel filter error signal to a pulse-width modulator which generates drive signals for said parallel filter inverter.

Claim 43

The method of claim 25 further comprising the steps of: continuously producing an instantaneous vector sum for first and second serial inverter input voltage signals; sequentially establishing from said first and second serial inverter input voltage signals a plurality of relative phase values e between said voltage signals; selecting one of said relative phase values Θ to form a selected phase value; and defining a sin Θ and a cos Θ value corresponding to said selected phase value.