Bus lock control apparatus capable of controlling without stopping bus arbiters

Claim 1

A bus lock control apparatus having a common bus, a plurality of agents connected to said common bus and a single bus arbiter, said single bus arbiter being connected to receive initial resource use request signals one by one from each of said agents and to send bus use enable signals one by one to each of said agents, to receive initial resource use requests from each of said agents and to send a bus use enable signal only to one specific agent serving as a bus master agent, to utilize resources connected to said bus, the lock control apparatus comprising: a monitor manager for acknowledging a bus lock request, a bus lock release request and a requesting agent from a resource use request sent to address command lines in said common bus from said agent serving as a bus master, and outputting to each agent a set signal in the case of a bus lock request and a reset signal in the case of a bus lock release request, said bus arbiter having a register means comprising a plurality of bits corresponding to a plurality of agents for registering bus lock enable information in accordance with a set or reset signal from said monitor manager, and an OR circuit for executing a logical sum for all information bits of said register means, said common bus having a lock acknowledging means for connecting an output of said OR circuit to all said agents in a single line, and each one of said agents having a delay circuit for delaying a bus use enable signal from said bus arbiter for a constant period of time, and a lock indicator means inputting an output of the delay circuit and a bus lock/bus lock release signal and for latching a logical complement of the content of said lock acknowledging means in said common bus, when the output of said delay circuit and said bus lock/bus lock release signal are valid, said bus lock/bus lock release signal being outputted from a request controller outputting a resource use request signal to address command lines in said common bus; wherein said delay circuit generates a timing signal one clock faster than a timing of said lock acknowledging means in said common bus, by means of said a bus use enable signal from said bus arbiter, and an agent having a lock indicator means for latching a logical complement of the content of the lock acknowledging means in said common bus when said bus lock/bus lock release signal from said request controller and a signal from said delay circuit become valid.