US5353027A
Expired / Lapsed
US
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Multistep analog-to-digital converter with error correction
Assignee: NXP BV
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Filing: 1992-10-26
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Granted: 1994-10-04
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Expires: 2012-10-26
Abstract
Abstract A sub-ranging analog-to-digital converter includes, in cascade, a coarse converter, a digital-to-analog converter, a subtracter circuit and a fine converter. Errors of the coarse converter are detected in the fine converter by means of an overflow detector and an underflow detector which generate an overflow signal (OF) and an underflow signal (UF), respectively. The digital output (D A ) of the coarse converter is corrected by first subtracting one LBS in a decoder and then, in response to the overflow and underflow signal, adding thereto zero, one or two LBSs.
Inventors
- 👤 Pieter P. M. Vorenkamp
- 👤 Johannes Verdaasdonk
- 👤 Marcellinus J. M. Pelgrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:13
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/069; H03M1/12; H03M1/14; H03M1/145
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
236 words
Analog-to-digital converter comprising: a first analog-to-digital converter for converting a first analog signal (U 1 ) to a first digital signal (D A ) which denotes from a plurality of sub-ranges a sub-range in which the first analog signal is situated, a digital-to-analog converter for converting the first digital signal to a second analog signal (U 2 ), a second analog-to-digital converter (5) for converting a difference signal (U 3 ) indicative of the difference between the first and second analog signals (U 1 , U 2 ) to a second digital signal (D B ), detection means for detecting an overflow (OF) and an underflow (UF) if the difference signal is situated above and below respectively, the sub-range denoted by the first digital signal, correction means for correcting the first digital signal (D A ) in response to the detection of the overflow (OF) and underflow (UF), wherein the correction means comprise: means for generating a third digital signal (D C ) which represents a value that is one least significant bit less than the value represented by the first digital signal (D A ), adder means for adding to the third digital signal (D C ) zero and two least significant bits respectively, in the case of a detection of the underflow (UF) and overflow (OF) respectively, and one least significant bit in the case of detection of neither an underflow or an overflow.
Claim 2
Dependent Claim
236 words
Analog-to-digital converter comprising: a first analog-to-digital converter for converting a first analog signal (U 1 ) to a first digital signal (D A ) which denotes from a plurality of sub-ranges a sub-range in which the first analog signal is situated, a digital-to-analog converter for converting the first digital signal to a second analog signal (U 2 ), a second analog-to-digital converter (5) for converting a difference signal (U 3 ) indicative of the difference between the first and second analog signals (U 1 , U 2 ) to a second digital signal (D B ), detection means for detecting an overflow (OF) and an underflow (UF) if the difference signal is situated above and below respectively, the sub-range denoted by the first digital signal, correction means for correcting the first digital signal (D A ) in response to the detection of the overflow (OF) and underflow (UF), wherein the correction means comprise: means for generating a third digital signal (D C ) which represents a value that is one least significant bit less than the value represented by the first digital signal (D A ), adder means for adding to the third digital signal (D C ) zero and two least significant bits respectively, in the case of a detection of the underflow (UF) and overflow (OF) respectively, and one least significant bit in the case of detection of neither an underflow or an overflow.
Claim 3
Dependent Claim
60 words
Analog-to-digital converter as claimed in claim 1, wherein the first analog-to-digital converter comprises a decoder for decoding an internal digital signal having an internal code to the first digital signal (D A ) having an external code which differs from the internal code, and in that the generating means for generating the third digital signal are included in the decoder.
Claim 4
Dependent Claim
46 words
Analog-to-digital converter as claimed in claim 2, wherein the external code of the first digital signal (D A ) is equal to the internal code of the first analog-to-digital converter and the digital-to-analog converter is arranged to receive a digital input signal having the internal code.
Claim 5
Dependent Claim
31 words
An analog-to-digital converter as claimed in claim 1 further comprising, means responsive to the first analog signal and to the second analog signal for deriving said difference signal (U 3 ).
Claim 6
Dependent Claim
59 words
An analog-to-digital converter as claimed in claim 4 wherein outputs of the detection means are coupled to control input means of the adder means and output means of the adder means supply the most significant bits of the digital output signal and output means of the second analog-to-digital converter supply the least significant bits of the digital output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |