Method and apparatus for charging storage batteries to full capacity

Claim 2

A charging method for a storage battery, in particular for NiCd (nickel cadmium) and NiH (nickel hydride) cells comprising the following steps: connecting said battery to a charging current source; cyclically separating said charging current source from said battery for a certain period in order to generate measurement intervals; during said measurement intervals, cyclically comparing a measured charging voltage with a stored reference value; if the value of said charging voltage has an actual value greater than said reference value, increasing said reference value by a certain amount to match the reference value to the actual value of said charging voltage and then storing the increased reference value; counting the number of measurement intervals in which the measured charging voltage is consecutively equal to or less than the stored reference value; finally switching off said charging current source or reducing charging current at a preset count; and wherein said step of counting includes providing an up-down counter and setting the counter at the start of a charging operation to its highest or lowest reading, when the increased reference value is stored, switching said up-down counter to its up mode or down mode, respectively, and switching said up-down counter to its down mode or up mode, respectively, if the actual value of said charging voltage is less than said stored reference value.

Claim 3

A method according to claim 1, wherein said charging current (I L ) is set depending on the count of said up-down counter.

Claim 4

A method according to claim 2, wherein said charging current (I L ) is reduced step by step depending on said count.

Claim 5

A circuit array for charging a storage battery, in particular for NiCd (nickel cadmium) and NiH (nickel hydride) cells, comprising: a charging current source for connection to a battery; means for cyclically separating said charging current source from said battery for a certain period of time in order to generate measurement intervals; means for cyclically comparing a charging voltage at the source with a stored reference value during said measurement intervals and, if the value of said charging voltage is greater than said reference value, for increasing said reference value by a certain amount to match said reference value to an actual measured value of said charging voltage and for then storing the increased reference value, said means for comparing including a peak value memory and a pulse generator for generating a clock signal for said peak value memory; means for counting the number of measurement intervals in which the value of the measured charging voltage is consecutively equal to or less than the stored reference value, with said means for counting including an up-down counter that is set at the start of a charging operation to the highest or lowest count and logic circuit means, controlled by comparison results from said peak value memory, for switching said up-down counter into its up mode or down mode, respectively, when the increased reference value is stored, and for switching said up-down counter into its down mode or up mode, respectively, when the actual value of said charging voltage is less than said stored reference value; and, means, responsive to a preset count in said up-down counter, for switching off said charging current source or for reducing charging current step by step depending on said count in said counter, said means for switching including a D/A converter connected behind said up-down counter and supplying a control voltage corresponding to said count of said up-down counter to said charging current source to control the charging current.

Claim 6

A circuit array for charging a storage battery, in particular for NiCd (nickel cadmium) and NiH (nickel hydride) cells, comprising: a charging current source for connection to a battery; means for cyclically separating said charging current source from said battery for a certain period of time in order to generate measurement intervals; means for cyclically comparing a charging voltage at the source with a stored reference value during said measurement intervals and, if the value of said charging voltage is greater than said reference value, for increasing said reference value by a certain amount to match said reference value to an actual measured value of said charging voltage and for then storing the increased reference value, said means for comparing including a peak value memory and a pulse generator for generating a clock signal for said peak value memory; means for counting the number of measurement intervals in which the value of the measured charging voltage is consecutively equal to or less than the stored reference value, with said means for counting including an up-down counter that is set at the start of a charging operation to the highest or lowest count and logic circuit means, controlled by comparison results from said peak value memory, for switching said up-down counter into its up mode or down mode, respectively, when the increased reference value is stored, and for switching said up-down counter into its down mode or up mode, respectively, when the actual value of said charging voltage is less than said stored reference value; and, means, responsive to a preset count in said up-down counter, for switching off said charging current source or for reducing charging current step by step depending on said count in said counter, said means for switching including a D/A converter connected behind said up-down counter and supplying a control voltage corresponding to said count of said up-down counter to said charging current source to control the charging current.

Claim 7

A circuit array according to claim 4, wherein means are provided to supply said peak value memory with only one cycle per measurement interval in the event that said reference value stored in said peak value memory is less than the value of said actual charging voltage by a preset minor amount.

Claim 8

A circuit array according to claim 5, wherein a shift register is connected in front of a V input of said up-down counter.

Claim 9

A circuit array according to claim 6, wherein a further shift register is connected in front of an R input of said up-down counter.

Claim 10

A circuit array according to claim 7, wherein said peak value memory controls said up-down counter to switch into the down mode or the up mode respectively only when said actual charging voltage has dropped by a certain minor amount below the stored reference value.