Detent switching of summing node capacitors of a delta-sigma modulator

Claim 2

A delta-sigma modulator for receiving an analog input signal and providing a digital output signal comprising: a) a summing node for summing the input signal and a feedback signal; b) an integrator for integrating the signal at said summing node; c) a loop filter for filtering the signal out of said integrator; d) a quantizer for digitizing the signal out of said loop filter, the output of the quantizer forming the digital output of the modulator; and e) a first switched capacitor circuit having a first capacitor coupled between an input terminal and an output terminal wherein the input terminal is switched to N different increasing voltages or N different decreasing voltages during a sampling period in response to said digital output of the modulator, where N is greater than 2, and the output terminal is switched between a reference voltage and said feedback signal once during said sampling period whereby the voltage stress across the output terminal during each switch to a different voltage is reduced compared to the stress which would occur if the contact were switched directly from the first of said N voltages directly to the last of said N voltages.

Claim 3

A delta-sigma modulator as set forth in claim 1 which further includes a second switched capacitor circuit having a second capacitor coupled between an input terminal and an output terminal wherein the input terminal is coupled to a different voltage N times during said sampling period in response to said digital output of the modulator, and the output terminal being switched between a reference voltage and said feedback signal once during said sampling period.

Claim 4

A delta-sigma modulator for receiving an analog input signal and providing a digital output signal comprising: a) a summing node for summing the input signal and a feedback signal; b) an integrator for integrating the signal at said summing node; c) a loop filter for filtering the signal out of said integrator; d) a quantizer for digitizing the signal out of said loop filter, the output of the quantizer forming the digital output of the modulator; and e) a first switched capacitor feedback circuit comprising: i) a three position switch having a first position coupled to a positive reference voltage, a second switch position coupled to ground, and a third position coupled to a negative reference voltage; ii) a feedback capacitor having a first terminal coupled to the pole of the said three position switch; and iii) a two position switch having a pole coupled to the second terminal of said capacitor, a first position coupled to ground and a second position coupled to said summing node.

Claim 5

A delta-sigma modulator for receiving an analog input signal and providing a digital output signal comprising: a) a summing node for summing the input signal and a feedback signal; b) an integrator for integrating the signal at said summing node; c) a loop filter for filtering the signal out of said integrator; d) a quantizer for digitizing the signal out of said loop filter, the output of the quantizer forming the digital output of the modulator; and e) a first switched capacitor feedback circuit comprising: i) a three position switch having a first position coupled to a positive reference voltage, a second switch position coupled to ground, and a third position coupled to a negative reference voltage; ii) a feedback capacitor having a first terminal coupled to the pole of the said three position switch; and iii) a two position switch having a pole coupled to the second terminal of said capacitor, a first position coupled to ground and a second position coupled to said summing node.

Claim 6

The delta-sigma modulator set forth in claim 3 wherein said three position switch sequences from said first position to said second position to said third position when the output of said quantizer is at a first level, and said three position which sequences from said third position to said second position to said first position when the output of said quantizer is at a second level.

Claim 7

A delta-sigma modulator set forth in claim 3 further including a second switched capacitor circuit comprising: i) a three position switch having a first position coupled to a positive reference voltage, a second switch position coupled to ground, and a third position coupled to a negative reference voltage; ii) a feedback capacitor having a first terminal coupled to the pole of the said three position switch; and iii) a two position switch having a pole coupled to the second terminal of said capacitor, a first position coupled to ground and a second position coupled to said summing node; and wherein said first three position switch sequences from said first position to said second position to said third position in each sampling period and said second three position switch sequences from said third position to said second position to said first position in each sampling period and both of said first and second two position switches either remain in said first position during the sampling period or sequenced from said first position to said second position during the sampling period as determined by the output of said quantizer.

Claim 10

In a delta-sigma modulator having a switched feedback capacitor which provides a charge to a summing node during a sample period, the improvement comprising providing a charge to said summing node from said feedback capacitor at two different times during said sample period.

Claim 11

In a delta-sigma modulator having a switched feedback capacitor which provides a charge to a summing node during a sample period, the improvement comprising providing a charge to said summing node from said feedback capacitor at two different times during said sample period.

Claim 12

The improvement set forth in claim 7 wherein said charge transferred during said two different times are of equal magnitude.

Claim 13

A switched capacitor integrator having positive and negative input terminals and positive and negative output terminals comprising: a) a differential amplifier having a negative output coupled to the positive output terminal, and a positive output coupled to the negative output terminal; a) a first switched capacitor circuit having a first capacitor coupled between an input lead and an output lead wherein the input lead is coupled sequentially to the positive input terminal, a common mode voltage, and the negative input terminal during a sampling period, and the output lead is switched between a reference voltage and a positive input of said differential amplifier once during said sampling period; b) a second switched capacitor circuit having a second capacitor coupled between an input lead and an output lead wherein the input lead is coupled sequentially to the negative input terminal, a common mode voltage, and the positive input terminal during a sampling period, and the output lead is switched between a reference voltage and a negative input of said differential amplifier once during said sampling period; c) a third capacitor coupled between said negative output of said differential amplifier and said positive input of said differential amplifier; and e) a fourth capacitor coupled between said positive output of said differential amplifier and said negative input of said differential amplifier.

Claim 14

A switched capacitor integrator having positive and negative input terminals and positive and negative output terminals comprising: a) a differential amplifier having a negative output coupled to the positive output terminal, and a positive output coupled to the negative output terminal; a) a first switched capacitor circuit having a first capacitor coupled between an input lead and an output lead wherein the input lead is coupled sequentially to the positive input terminal, a common mode voltage, and the negative input terminal during a sampling period, and the output lead is switched between a reference voltage and a positive input of said differential amplifier once during said sampling period; b) a second switched capacitor circuit having a second capacitor coupled between an input lead and an output lead wherein the input lead is coupled sequentially to the negative input terminal, a common mode voltage, and the positive input terminal during a sampling period, and the output lead is switched between a reference voltage and a negative input of said differential amplifier once during said sampling period; c) a third capacitor coupled between said negative output of said differential amplifier and said positive input of said differential amplifier; and e) a fourth capacitor coupled between said positive output of said differential amplifier and said negative input of said differential amplifier.

Claim 15

In a differential switched capacitor integrator having a pair of switched input capacitors which receive positive and negative input signals, respectively, and each of said switched input capacitors provide charge to the one of two inputs of a differential amplifier during each sample period, the improvement comprising providing charge from each of said switched input capacitors to said inputs of said differential amplifier at two different times during said sample period.

Claim 16

In a differential switched capacitor integrator having a pair of switched input capacitors which receive positive and negative input signals, respectively, and each of said switched input capacitors provide charge to the one of two inputs of a differential amplifier during each sample period, the improvement comprising providing charge from each of said switched input capacitors to said inputs of said differential amplifier at two different times during said sample period.

Claim 17

In a delta-sigma modulator having a switched capacitor which provides a charge to a summing node during each sample period, the improvement comprising providing a charge to said summing node from said capacitor at two different times during said sample period wherein the charges provided during said sample period are always either both positive or both negative.

Claim 18

In a delta-sigma modulator having a switched capacitor which provides a charge to a summing node during each sample period, the improvement comprising providing a charge to said summing node from said capacitor at two different times during said sample period wherein the charges provided during said sample period are always either both positive or both negative.

Claim 19

The improvement set forth in claim 11 wherein said switched capacitor is a feedback capacitor.