US5349349A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Modulator circuit for a recording for a digital recording medium
Assignee: Sony Corp
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Filing: 1992-09-17
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Granted: 1994-09-20
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Expires: 2012-09-17
Abstract
Abstract A modulator circuit is constructed such that an input signal is code converted, after an error code correction code is added thereto, into a channel bit pattern suitable for characteristics of a recording and reproducing system for recording and reproduction of digital data. Margin bits are inserted between adjacent channel bit patterns in order to limit the lengths of the channel bit patterns. One or ones of a plurality of predetermined margin bit patterns which are to be inhibited from being inserted between particular two channel bit patterns are determined in accordance with a predetermined algorithm referring to the second last, the last and the present channel bit patterns and the last margin bit pattern. The output of an integrating circuit for measuring a digital sum variation of a channel bit pattern signal and a channel bit pattern is provided with a saturation characteristic so that the output may not diverge. A margin bit generating circuit receives a signal regarding one or ones of the margin bit patterns which are to be inhibited from use, a controlling signal regarding a channel bit pattern placed prior to the margin bit pattern and a cumulative digital sum variation and another controlling signal regarding another cumulative digital sum variation of another channel bit pattern placed subsequent to the margin bit pattern, and the scale of the modulator circuit is reduced with the margin bit generating circuit.
Inventors
- 👤 Kazutoshi Shimizume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:12
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; H; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; G11B2020/1461; G11B2020/1469
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A modulator circuit wherein each input m-bit code is modulated into an n-channel bit pattern, n being greater than m, and two adjacent ones of such n-channel bit patterns are coupled to each other using one of a plurality of margin bit patterns to limit the longest and shortest recording wavelengths while suppressing low band components of a recording waveform, comprising: a first logic circuit for adding an n-bit false frame synchronizing signal having a bit pattern at least part of which is the same as part of a frame synchronizing signal in order to achieve unified judgment of an inhibited margin bit patterns out of said plurality of margin bit patterns; and a second logic circuit for referring to the second last, the last and present n-channel bit patterns and the last margin bit pattern to judge an inhibited margin bit patterns in accordance with a predetermined algorithm and outputting an inhibition signal representative of the thus judged margin bit pattern out of said plurality of margin bit patterns.
Claim 2
Dependent Claim
170 words
A modulator circuit wherein each input m-bit code is modulated into an n-channel bit pattern, n being greater than m, and two adjacent ones of such n-channel bit patterns are coupled to each other using one of a plurality of margin bit patterns to limit the longest and shortest recording wavelengths while suppressing low band components of a recording waveform, comprising: a first logic circuit for adding an n-bit false frame synchronizing signal having a bit pattern at least part of which is the same as part of a frame synchronizing signal in order to achieve unified judgment of an inhibited margin bit patterns out of said plurality of margin bit patterns; and a second logic circuit for referring to the second last, the last and present n-channel bit patterns and the last margin bit pattern to judge an inhibited margin bit patterns in accordance with a predetermined algorithm and outputting an inhibition signal representative of the thus judged margin bit pattern out of said plurality of margin bit patterns.
Claim 3
Dependent Claim
93 words
A modulator circuit according to claim 1, further comprising: a digital sum variation measuring circuit for receiving an output signal of said modulator circuit and measuring a digital sum variation of each margin bit pattern and an n-channel bit pattern following the margin bit pattern; and an integrating circuit for receiving an output signal of said digital sum variation measuring circuit, integrating the digital sum variation with a finite dc gain to obtain a controlling signal regarding a cumulative digital sum variation and outputting the controlling signal to a margin bit generating circuit.
Claim 4
Dependent Claim
93 words
A modulator circuit according to claim 1, further comprising: margin bit generating means for receiving a signal regarding an inhibited margin bit patterns, a controlling signal regarding a last recording waveform level of an n-channel bit pattern placed prior to the margin bit pattern, another controlling signal regarding a cumulative digital sum variation and another controlling signal regarding another cumulative digital sum variation of another n-channel bit pattern placed subsequent to the margin bit pattern and outputting an optimum margin bit pattern from among said margin bit patterns decisively with a logic circuit.
Claim 5
Dependent Claim
322 words
A modulator circuit wherein each input m-bit code is modulated into an n-channel bit pattern, n being greater than m, and two adjacent ones of such n-channel bit patterns are coupled to each other using one of a plurality of margin bit patterns to limit the longest and shortest recording wavelengths while suppressing low band components of a recording waveform, comprising: a first logic circuit for adding an n-bit false frame synchronizing signal having a bit pattern at least part of which is the same as part of a frame synchronizing signal in order to achieve unified judgment of at least one inhibited margin bit pattern out of said plurality of margin bit patterns; a second logic circuit for referring to the second last, the last and present n-channel bit patterns and the last margin bit pattern to judge at least one inhibited margin bit pattern in accordance with a predetermined algorithm and outputting an inhibition signal representative of the thus judged margin bit pattern out of said plurality of margin bit patterns; a digital sum variation measuring circuit for receiving an the inhibition signal, measuring a digital sum variation of each margin bit pattern and an n-channel bit pattern following the margin bit pattern and generating an output signal; an integrating circuit for receiving the output signal of said digital sum variation measuring circuit, integrating the digital sum variation with a finite dc gain to generate a controlling signal regarding a cumulative digital sum variation; and margin bit generating means for receiving the controlling signal regarding a cumulative digital sum variation, a controlling signal regarding a last recording waveform level of an n-channel bit pattern placed prior to the margin bit pattern, and a controlling signal regarding another cumulative digital sum variation of another n-channel bit pattern placed subsequent to the margin bit pattern and outputting from a logic circuit an optimum margin bit pattern from among said margin bit patterns.
Claim 6
Dependent Claim
322 words
A modulator circuit wherein each input m-bit code is modulated into an n-channel bit pattern, n being greater than m, and two adjacent ones of such n-channel bit patterns are coupled to each other using one of a plurality of margin bit patterns to limit the longest and shortest recording wavelengths while suppressing low band components of a recording waveform, comprising: a first logic circuit for adding an n-bit false frame synchronizing signal having a bit pattern at least part of which is the same as part of a frame synchronizing signal in order to achieve unified judgment of at least one inhibited margin bit pattern out of said plurality of margin bit patterns; a second logic circuit for referring to the second last, the last and present n-channel bit patterns and the last margin bit pattern to judge at least one inhibited margin bit pattern in accordance with a predetermined algorithm and outputting an inhibition signal representative of the thus judged margin bit pattern out of said plurality of margin bit patterns; a digital sum variation measuring circuit for receiving an the inhibition signal, measuring a digital sum variation of each margin bit pattern and an n-channel bit pattern following the margin bit pattern and generating an output signal; an integrating circuit for receiving the output signal of said digital sum variation measuring circuit, integrating the digital sum variation with a finite dc gain to generate a controlling signal regarding a cumulative digital sum variation; and margin bit generating means for receiving the controlling signal regarding a cumulative digital sum variation, a controlling signal regarding a last recording waveform level of an n-channel bit pattern placed prior to the margin bit pattern, and a controlling signal regarding another cumulative digital sum variation of another n-channel bit pattern placed subsequent to the margin bit pattern and outputting from a logic circuit an optimum margin bit pattern from among said margin bit patterns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |