US5348902A
Expired / Lapsed
US
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Method of designing cells applicable to different design automation systems
Assignee: Renesas Electronics Corp
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Filing: 1993-01-19
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Granted: 1994-09-20
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Expires: 2013-01-19
Abstract
Abstract In a method of designing cells applicable to different first and second design automation systems, first and second cells circuit-designed by the first and second design automation systems, respectively, are demarcated into a logic function portion and an input/output portion. A plurality of sets of common lithography patterns for the logic function portions of the first and second cells are determined such that each common lithography pattern set is shared by those of the first and second cells which have same logic function in the first and second design automation systems. A first set of lithography patterns for the input/output portions of the first cells in the first design automation system and a second set of lithography patterns for the input/output portions of the second cells in the second design automation system are determined, respectively. The first and second sets of lithography patterns are, at their external ends, in an arrangement satisfying requirements of the first and second design automation systems, respectively. The logic function portion of one or more of the first cells in the first design automation system having the determined set of common lithography pattern is combined with the input/output portion of the second cells having the second set of lithography pattern in the second design automation system.
Inventors
- 👤 Shigeru Shimada
- 👤 Ryuji Shibata
- 👤 Atsushi Kurosawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:23
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
269 words
A method of designing first and second cells applicable to different first and second design automation systems as a part of a circuit design, comprising: preparing the first cells circuit-designed by the first design automation system and the second cells circuit-designed by the second design automation system; demarcating each of said first and second cells into a logic function portion and an input/output portion, wherein said logic function portion is responsible for a logic function of the circuit design and said input/output portion is responsible for an arrangement of input/output conductors for electrical connection of the circuit design; determining a plurality of sets of common lithography patterns for the logic function portions of said first and second cells such that each common lithography pattern set is shared by those of said first and second cells which have same logic function in said first and second design automation systems; determining a first set of lithography patterns for the input/output portions of said first cells in said first design automation system and a second set of lithography patterns for the input/output portions of said second cells in said second design automation system, respectively, such that said first and second sets of lithography patterns are, at their external ends, in an arrangement satisfying requirements of said first and second design automation systems, respectively; and combining the logic function portion of at least one of said first cells in said first design automation system having said determined set of common lithography pattern, with the input/output portion of said second cells having said second set of lithography pattern in said second design automation system.
Claim 2
Independent Claim
269 words
A method of designing first and second cells applicable to different first and second design automation systems as a part of a circuit design, comprising: preparing the first cells circuit-designed by the first design automation system and the second cells circuit-designed by the second design automation system; demarcating each of said first and second cells into a logic function portion and an input/output portion, wherein said logic function portion is responsible for a logic function of the circuit design and said input/output portion is responsible for an arrangement of input/output conductors for electrical connection of the circuit design; determining a plurality of sets of common lithography patterns for the logic function portions of said first and second cells such that each common lithography pattern set is shared by those of said first and second cells which have same logic function in said first and second design automation systems; determining a first set of lithography patterns for the input/output portions of said first cells in said first design automation system and a second set of lithography patterns for the input/output portions of said second cells in said second design automation system, respectively, such that said first and second sets of lithography patterns are, at their external ends, in an arrangement satisfying requirements of said first and second design automation systems, respectively; and combining the logic function portion of at least one of said first cells in said first design automation system having said determined set of common lithography pattern, with the input/output portion of said second cells having said second set of lithography pattern in said second design automation system.
Claim 3
Dependent Claim
98 words
A method according to claim 1, wherein said second set of lithography patterns for the input/output portions of the second cells is, at its internal end, in an arrangement consistent with an arrangement of an end of said common lithography pattern set for said logic function portion of said one first cell in said first design automation system, said combining step includes replacing an input/output portion of said one first cell in said first design automation system by said input/output portion of the second cells having said second set of lithography patterns in said second design automation system.
Claim 4
Dependent Claim
67 words
A method according to claim 2, wherein said replacing step includes extracting said logic function portion from said at least one first cell in said first design automation system and attaching said input/output portion of said second cells having said second set of lithography pattern in said second design automation system to said extracted logic function portion of the first cell in said first design automation system.
Claim 5
Dependent Claim
23 words
A method according to claim 1, wherein said arrangement of input/output conductors includes a layout pitch and layout levels of said input/output conductors.
Claim 6
Dependent Claim
33 words
A method according to claim 4, wherein said arrangement of input/output conductors further includes interconnection between input/output conductors of said input/output portions and connection conductors in said logic function portions at different levels.
Claim 7
Independent Claim
191 words
A method of designing first and second cells applicable to different first and second design automation systems as a part of a circuit design, comprising: preparing the first cells circuit-designed by the first design automation system and the second cells circuit-designed by second design automation system; demarcating each of said first and second cells into a logic function portion and an input/output portion, wherein said logic function portion is responsible for a logic function defined by the circuit design and said input/output portion is responsible for an arrangement of input/output conductors for electrical connection with another cell; determining a set of lithography patterns for the input/output portions of said second cells in said second design automation such that said set of lithography patterns is, at its external end, in an arrangement satisfying requirement of said second design automation system and is, at its internal end, in an arrangement satisfying requirement of said first design automation system, respectively; and attaching said input/output portion of said second cells having said determined set of lithography pattern in said second design automation system to at least one first cell in said first design automation system.
Claim 8
Independent Claim
191 words
A method of designing first and second cells applicable to different first and second design automation systems as a part of a circuit design, comprising: preparing the first cells circuit-designed by the first design automation system and the second cells circuit-designed by second design automation system; demarcating each of said first and second cells into a logic function portion and an input/output portion, wherein said logic function portion is responsible for a logic function defined by the circuit design and said input/output portion is responsible for an arrangement of input/output conductors for electrical connection with another cell; determining a set of lithography patterns for the input/output portions of said second cells in said second design automation such that said set of lithography patterns is, at its external end, in an arrangement satisfying requirement of said second design automation system and is, at its internal end, in an arrangement satisfying requirement of said first design automation system, respectively; and attaching said input/output portion of said second cells having said determined set of lithography pattern in said second design automation system to at least one first cell in said first design automation system.
Claim 9
Independent Claim
153 words
A method of designing first and second cells as a part of circuit design, comprising: preparing the first and second cells for which the circuit design has been completed, said first and second cells having an identical number of input/output terminals; demarcating each of said first and second cells into a logic function portion and an input/output portion, wherein said logic function portion is responsible for a logic function defined by the circuit design and said input/output portion is responsible for an arrangement of input/output conductors for electrical connection with another cell; determining a common lithography pattern for an interface portion including adjoining parts of said logic function portion and said input/output portion of said first and second cells such that said common lithography pattern is shared by said first and second cells; and determining a set of lithography patterns for each of said logic function portions of said first and second cells.
Claim 10
Independent Claim
153 words
A method of designing first and second cells as a part of circuit design, comprising: preparing the first and second cells for which the circuit design has been completed, said first and second cells having an identical number of input/output terminals; demarcating each of said first and second cells into a logic function portion and an input/output portion, wherein said logic function portion is responsible for a logic function defined by the circuit design and said input/output portion is responsible for an arrangement of input/output conductors for electrical connection with another cell; determining a common lithography pattern for an interface portion including adjoining parts of said logic function portion and said input/output portion of said first and second cells such that said common lithography pattern is shared by said first and second cells; and determining a set of lithography patterns for each of said logic function portions of said first and second cells.
Claim 11
Dependent Claim
56 words
A method of manufacturing a semiconductor integrated circuit device comprising the steps of: placing and routing the first and second cells designed by the method defined by claim 1 to produce mask pattern information; preparing mask patterns from said mask pattern information; and forming semiconductor devices in a semiconductor substrate by use of said mask patterns.
References Cited (Backward Citations)
EP0126525A1
Cited
US5124273A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |