US5347710A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel processor and method of fabrication
Assignee: International Business Machines Corp
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Filing: 1993-07-27
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Granted: 1994-09-20
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Expires: 2013-07-27
Abstract
Abstract Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.
Inventors
- 👤 Thomas P. Gall
- 👤 Howard L. Heck
- 👤 John S. Kresge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:49
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4611; H05K3/4626; H05K3/4635; H05K3/4614; H05K3/462; H05K1/00; H05K1/02; H05K1/03; H05K1/0313; H05K1/0353; H05K1/0373; H05K1/0393; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/015; H05K2201/0154; H05K2201/09; H05K2201/09009; H05K2201/09109; H05K2201/09209; H05K2201/095; H05K2201/09536; H05K2201/10; H05K2201/10007; H05K2201/10159; H05K3/4623; H05K3/4641; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49155
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
444 words
A method of fabricating a parallel processor structure having a plurality of processor integrated circuit chips, a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon; b. said printed circuit cards and boards are mounted on a plurality of circuitized flexible strips, said circuitized flexible strips having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and c. said circuitized flexible strips being joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible strips at their signal interconnection circuitization portions, whereby said circuitized flexible strips are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions; said process comprising a. forming first and second laminates of copper, a dielectric, and a low coefficient of thermal expansion metal; b. photolithographically forming patterns in said copper and said low coefficient of thermal expansion metal layers; c. bonding the first and second laminates together; d. thereafter forming vias and through holes in said bonded first and second laminates, and circuitizing said vias and through holes. e. depositing joining metallurgy on said bonded laminates; and f. aligning at least a pair of bonded laminates with a layer of a chemically compatible polymeric dielectric with a relatively low first thermal transition therebetween in areas between a pair of laminates intended to be bonded and a layer of a chemically incompatible polymeric dielectric with a relatively high first thermal transition therebetween in areas between the laminates not intended to be bonded, and thermally bonding the laminates above the eutectic temperature of the joining metallurgy and the first thermal transition temperature of the chemically compatible dielectric and below the homogenized alloy melting temperature of the joining metallurgy and the first thermal transition temperature of the joining metallurgy.
Claim 2
Independent Claim
444 words
A method of fabricating a parallel processor structure having a plurality of processor integrated circuit chips, a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon; b. said printed circuit cards and boards are mounted on a plurality of circuitized flexible strips, said circuitized flexible strips having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and c. said circuitized flexible strips being joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible strips at their signal interconnection circuitization portions, whereby said circuitized flexible strips are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions; said process comprising a. forming first and second laminates of copper, a dielectric, and a low coefficient of thermal expansion metal; b. photolithographically forming patterns in said copper and said low coefficient of thermal expansion metal layers; c. bonding the first and second laminates together; d. thereafter forming vias and through holes in said bonded first and second laminates, and circuitizing said vias and through holes. e. depositing joining metallurgy on said bonded laminates; and f. aligning at least a pair of bonded laminates with a layer of a chemically compatible polymeric dielectric with a relatively low first thermal transition therebetween in areas between a pair of laminates intended to be bonded and a layer of a chemically incompatible polymeric dielectric with a relatively high first thermal transition therebetween in areas between the laminates not intended to be bonded, and thermally bonding the laminates above the eutectic temperature of the joining metallurgy and the first thermal transition temperature of the chemically compatible dielectric and below the homogenized alloy melting temperature of the joining metallurgy and the first thermal transition temperature of the joining metallurgy.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein the low coefficient of thermal expansion metal is chosen from the group consisting of copper, molybdenum, and Copper-Invar-Copper laminates.
Claim 4
Dependent Claim
83 words
The method of claim 1 comprising bonding said laminates together by a process comprising the steps of: i. positioning the two said laminates with their copper surfaces facing outward, ii. providing a layer of a chemically compatible polymeric dielectric with a relatively low first thermal transition therebetween in areas intended to be bonded and a layer of a chemically incompatible polymeric dielectric with a relatively high first thermal transition therebetween in areas not intended to be bonded, and iii. thermally bonding the laminates.
Claim 5
Dependent Claim
14 words
The method of claim 3 comprising applying a layer of dielectric atop the copper.
Claim 6
Dependent Claim
14 words
The method of claim 4 comprising applying a sacrificial copper foil atop the dielectric.
Claim 7
Dependent Claim
37 words
The method of claim 1 wherein said bonding metallurgy has a eutectic temperature below the first thermal transition temperature of the dielectric and a homogenized alloy melting temperature above the first thermal transition temperature of the dielectric.
Claim 8
Dependent Claim
54 words
The method of claim 1 wherein the dielectric is a perfluorocarbon polymer, comprising providing a low melting adhesive chemically compatible with the perfluorocarbon polymer between the laminates in the regions intended to be laminated, and thereafter stacking a first laminate above a second laminate and heating the laminate stack to effect adhesion and lamination.
Claim 9
Dependent Claim
19 words
The method of claim 7 wherein the low melting adhesive compatible with the perfluorocarbon polymer is a thermoplastic polyimide.
Claim 10
Dependent Claim
22 words
The method of claim 8 wherein the thermoplastic polyimide is chosen from the group consisting of BTDA-ODA-MPD, BPDA-6FDAM, and Pyralin 2566 6FDA-ODA.
Claim 11
Dependent Claim
65 words
The method of claim 7 comprising providing a high melting mask compatible with the perfluorocarbon polymer between the laminates in the regions not intended to be laminated, and thereafter stacking a first laminate above a second laminate and heating the laminate stack to selective effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
Claim 12
Dependent Claim
14 words
The method of claim 7 wherein the high melting mask is BPDA-PDA polyamic acid.
Claim 13
Dependent Claim
31 words
The method of claim 11 comprising drawing down the BPDA-PDA polyamic acid onto surfaces of the dielectric not intended to be laminated, and thereafter curing the BPDA-PDA to the corresponding polyimide.
Claim 14
Dependent Claim
30 words
The method of claim 11 comprising applying the BPDA-PDA as a free standing film, and laminating the dielectric above the melting temperature of the dielectric but below its imidization temperature.
Claim 15
Dependent Claim
108 words
The method of claim 7 comprising a. providing a low melting adhesive compatible with the perfluorocarbon polymer between the laminates in the regions intended to be laminated, and thereafter stacking a first laminate above a second laminate and heating the laminate stack to effect adhesion and lamination; and b. providing a high melting mask compatible with the perfluorocarbon polymer between the laminates in the regions not intended to be laminated, and thereafter stacking a first laminate above a second laminate and heating the laminate stack to selective effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |