US5347515A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for global polling having contention-based address identification
Assignee: Pittway Corp
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Filing: 1992-03-27
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Granted: 1994-09-13
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Expires: 2012-03-27
Abstract
Abstract A plurality of serially addressable devices connected to transmit data to or from a central controller via a two-wire polling loop has a global poll capability. The transmissions of data are via a tri-level line signal to provide both power and data transmission on a two-wire line. Global polling is initiated by a preamble recognized by each device in the loop. The preamble is followed by a single bit sequence to allow the devices to signal the central controller that one or more devices will respond to the global poll. If one or more devices will respond to the global poll, a series of bit sequences is generated by the central controller equal to the number of bits that will be transmitted by the serially addressable device to transmit its address and status. In order that only a single device respond to a global poll, if two or more devices are in contention for control of the loop to transmit their message to the central controller, each device measures the voltage on the loop and drops out of contention if it measures a digital zero while it is trying to transmit a digital one in the address field.
Inventors
- 👤 Francis C. Marino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:13
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/407; H04L12/413; H04L12/4135; H04L12/02; H04L12/10; H04L12/403
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
237 words
A method of global polling in a loop having a plurality of serially addressable devices each having a unique address and being coupled to each other by a pair of wires, in which data is transferred from or to each device by means of a multi-voltage level line signal generated by a central controller, said method comprising: transmitting from said central controller a preamble signal for instituting global polling; transmitting from said central controller a plurality of bit intervals corresponding to a number of bits in an address for each device plus a number of bits in a message; self-identification by each device in contention for responding to said central controller, where any of said devices in said loop can respond to the poll and where said central controller does not know the addresses of the devices that will respond to the poll prior to the self-identification step, said self-identification step comprising providing a low impedance across output terminals of said device when an address bit is a first logic state and providing a high impedance across said output terminals when an address bit is a second logic state; monitoring the voltage level on said loop by each device in contention; ceasing said self-identification step by a device if, when said device provides said second logic state at said output terminals, said monitoring step indicates a voltage level corresponding to said first logic state on said loop.
Claim 2
Independent Claim
237 words
A method of global polling in a loop having a plurality of serially addressable devices each having a unique address and being coupled to each other by a pair of wires, in which data is transferred from or to each device by means of a multi-voltage level line signal generated by a central controller, said method comprising: transmitting from said central controller a preamble signal for instituting global polling; transmitting from said central controller a plurality of bit intervals corresponding to a number of bits in an address for each device plus a number of bits in a message; self-identification by each device in contention for responding to said central controller, where any of said devices in said loop can respond to the poll and where said central controller does not know the addresses of the devices that will respond to the poll prior to the self-identification step, said self-identification step comprising providing a low impedance across output terminals of said device when an address bit is a first logic state and providing a high impedance across said output terminals when an address bit is a second logic state; monitoring the voltage level on said loop by each device in contention; ceasing said self-identification step by a device if, when said device provides said second logic state at said output terminals, said monitoring step indicates a voltage level corresponding to said first logic state on said loop.
Claim 3
Dependent Claim
24 words
The method according to claim 1 wherein said first logic state is a digital 0 and said second logic state is a digital 1.
Claim 4
Dependent Claim
33 words
The method according to claim 1 wherein said preamble signal includes a bit sequence for transmitting a signal to said central controller indicating that at least one device will respond to the poll.
Claim 5
Dependent Claim
18 words
The method according to claim 3 wherein said preamble comprises two digital ones followed by said bit sequence.
Claim 6
Dependent Claim
266 words
In a loop having a plurality of serially addressable devices each having a unique address and being coupled to each other by a pair of wires, in which data is transferred from or to each device by means of a multi-voltage level line signal generated by a central controller, apparatus for global polling said devices comprising: means in said central controller for transmitting a preamble signal for instituting global polling; means in said central controller for transmitting a plurality of bit intervals corresponding to a number of bits in an address for each device plus a number of bits in a message; self-identifying means in each device in contention for responding to said central controller for identifying each device by said unique address, wherein any of said devices in said loop can respond to the poll and wherein said central controller does not know the addresses of the devices that will respond to the poll prior to said identification of each device by its unique address, said self-identifying means comprising means for providing a low impedance across output terminals of said device when an address bit is a first logic state and means for providing a high impedance across said output terminals when an address bit is a second logic state; means for monitoring the voltage level on said loop by each device in contention; means in said self-identifying means for terminating output of said device address if, when said device provides said second logic state at said output terminals, said monitoring means indicates a voltage level corresponding to said first logic state on said loop.
Claim 7
Dependent Claim
266 words
In a loop having a plurality of serially addressable devices each having a unique address and being coupled to each other by a pair of wires, in which data is transferred from or to each device by means of a multi-voltage level line signal generated by a central controller, apparatus for global polling said devices comprising: means in said central controller for transmitting a preamble signal for instituting global polling; means in said central controller for transmitting a plurality of bit intervals corresponding to a number of bits in an address for each device plus a number of bits in a message; self-identifying means in each device in contention for responding to said central controller for identifying each device by said unique address, wherein any of said devices in said loop can respond to the poll and wherein said central controller does not know the addresses of the devices that will respond to the poll prior to said identification of each device by its unique address, said self-identifying means comprising means for providing a low impedance across output terminals of said device when an address bit is a first logic state and means for providing a high impedance across said output terminals when an address bit is a second logic state; means for monitoring the voltage level on said loop by each device in contention; means in said self-identifying means for terminating output of said device address if, when said device provides said second logic state at said output terminals, said monitoring means indicates a voltage level corresponding to said first logic state on said loop.
Claim 8
Dependent Claim
23 words
Apparatus according to claim 5 wherein said first logic state is a digital 0 and said second logic state is a digital one.
Claim 9
Dependent Claim
32 words
Apparatus according to claim 5 wherein said preamble signal includes a bit sequence for transmitting a signal to said central controller indicating that at least one device will respond to the poll.
Claim 10
Dependent Claim
17 words
Apparatus according to claim 7 wherein said preamble comprises two digital ones followed by said bit sequence.
Claim 11
Dependent Claim
245 words
In a serially addressable device having a unique address for being coupled to other such devices by a two-wire loop in which data is transferred to or from each device by means of a multi-voltage level line signal generated by a central controller for said loop, means for global polling comprising: starting means responsive to a preamble signal for instituting global polling address means responsive to said starting means and a series of bit intervals generated by said central controller for generating a plurality of bits representing the unique address of said device, where any of said devices in said loop can respond to the poll and where said central controller does not know the addresses of the devices that will respond to the poll prior to the generation of said unique address, said address means comprising driver means for providing a low impedance across output terminals of said device when one of said address bits is a first logic state and for providing a high impedance across said output terminals when said address bit is a second logic state; monitoring means coupled to said loop for monitoring the voltage level on said loop during each bit sequences; stopping means responsive to said monitoring means for ceasing generation of address bits by said driver means if said driver means provides said second logic state at said output terminals and said monitoring means indicates a voltage level on said loop corresponding to said first voltage level.
Claim 12
Dependent Claim
245 words
In a serially addressable device having a unique address for being coupled to other such devices by a two-wire loop in which data is transferred to or from each device by means of a multi-voltage level line signal generated by a central controller for said loop, means for global polling comprising: starting means responsive to a preamble signal for instituting global polling address means responsive to said starting means and a series of bit intervals generated by said central controller for generating a plurality of bits representing the unique address of said device, where any of said devices in said loop can respond to the poll and where said central controller does not know the addresses of the devices that will respond to the poll prior to the generation of said unique address, said address means comprising driver means for providing a low impedance across output terminals of said device when one of said address bits is a first logic state and for providing a high impedance across said output terminals when said address bit is a second logic state; monitoring means coupled to said loop for monitoring the voltage level on said loop during each bit sequences; stopping means responsive to said monitoring means for ceasing generation of address bits by said driver means if said driver means provides said second logic state at said output terminals and said monitoring means indicates a voltage level on said loop corresponding to said first voltage level.
Claim 13
Dependent Claim
24 words
The device according to claim 9 wherein said first logic state is a digital 0 and said second logic state is a digital one.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |