US5347229A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power amplifier with harmonically trapped heterojunction bipolar transistor
Assignee: Texas Instruments Inc
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Filing: 1992-12-16
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Granted: 1994-09-13
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Expires: 2012-12-16
Abstract
Abstract Power amplifier operating at a fixed frequency or a narrow bandwidth and based upon a non-linear gain element. The power amplifier includes a resonant circuit operably connected to the non-linear gain element, the circuit being resonant at a harmonic of substantially the band center frequency of the non-linear gain element and being arranged to dissipate energy resulting from harmonic generation by the non-linear gain element during signal amplification. In a particular aspect of the power amplifier, resonant circuits comprising inductor-capacitor harmonic trap circuits tuned to different harmonics are placed at both the input and the output of a gallium arsenide heterojunction bipolar transistor HBT providing the non-linear gain element.
Inventors
- 👤 Charles Suckling
- 👤 Glenn Collinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:03
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F1/00; H03F1/32
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
156 words
A power amplifier for operation within a narrow bandwidth regime, said power amplifier comprising: a heterojunction bipolar transistor having a base, a collector and an emitter for providing a non-linear gain; an input terminal connected to the base of said heterojunction bipolar transistor for providing an input electrical signal thereto; an output terminal connected to the collector of said heterojunction bipolar transistor for providing an amplified output electrical signal; harmonic input trap circuit means interposed in the connection between said input terminal and the base of said heterojunction bipolar transistor and being resonant at a harmonic of substantially band center frequency; and harmonic output trap circuit means interposed in the connection between the collector of said heterojunction bipolar transistor and said output terminal; said harmonic input and output trap circuit means increasing the efficiency of the power amplifier by dissipating energy resulting from harmonic generation by said heterojunction bipolar transistor during amplification of the electrical signal.
Claim 2
Dependent Claim
156 words
A power amplifier for operation within a narrow bandwidth regime, said power amplifier comprising: a heterojunction bipolar transistor having a base, a collector and an emitter for providing a non-linear gain; an input terminal connected to the base of said heterojunction bipolar transistor for providing an input electrical signal thereto; an output terminal connected to the collector of said heterojunction bipolar transistor for providing an amplified output electrical signal; harmonic input trap circuit means interposed in the connection between said input terminal and the base of said heterojunction bipolar transistor and being resonant at a harmonic of substantially band center frequency; and harmonic output trap circuit means interposed in the connection between the collector of said heterojunction bipolar transistor and said output terminal; said harmonic input and output trap circuit means increasing the efficiency of the power amplifier by dissipating energy resulting from harmonic generation by said heterojunction bipolar transistor during amplification of the electrical signal.
Claim 3
Dependent Claim
75 words
A power amplifier as set forth in claim 1, wherein said harmonic input and output trap circuit means respectively include first and second resonant circuits tuned to different harmonics; the first resonant circuits of said harmonic input and output trap circuit means being tuned to the same first harmonic; and the second resonant circuits of said harmonic input and output trap circuit means being tuned to the same second harmonic different from the first harmonic.
Claim 4
Dependent Claim
77 words
A power amplifier as set forth in claim 2, wherein said first and second resonant circuits of said harmonic input and output trap circuit means include circuits resonant at an even harmonic of substantially band center frequency to provide a short circuit phase; and said first and second resonant circuits of said harmonic input and output trap circuit means include circuits resonant at an odd harmonic of substantially band center frequency to provide an open circuit phase.
Claim 5
Dependent Claim
38 words
A power amplifier as set forth in claim 3, wherein said first and second resonant circuits of each of said harmonic input and output trap circuit means are second harmonic trap circuits and third harmonic trap circuits respectively.
Claim 6
Dependent Claim
43 words
A power amplifier as set forth in claim 4, wherein said second harmonic trap circuits comprise series resonant inductor-capacitor circuits connected from the input of said heterojunction bipolar transistor to ground and from the output of said heterojunction bipolar transistor to ground respectively.
Claim 7
Dependent Claim
45 words
A power amplifier as set forth in claim 5, wherein said third harmonic trap circuits of said harmonic input and output trap circuit means respectively comprise parallel resonant inductor-capacitor circuits connected in series at the input and at the output of said heterojunction bipolar transistor.
Claim 8
Dependent Claim
37 words
A power amplifier as set forth in claim 4, wherein said harmonic input trap circuit means further includes a third resonant circuit tuned to a different harmonic than the harmonics of said first and second resonant circuits.
Claim 9
Dependent Claim
27 words
A power amplifier as set forth in claim 7, wherein said third resonant circuit of said harmonic input trap circuit means is a fourth harmonic trap circuit.
Claim 10
Dependent Claim
21 words
A power transistor as set forth in claim 1, wherein said heterojunction bipolar transistor is a GaAs monolithic heterojunction bipolar transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |