US5345559A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus interface circuit for controlling data transfer
Assignee: Fujitsu Ltd
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Filing: 1990-11-28
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Granted: 1994-09-06
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Expires: 2010-11-28
Abstract
Abstract A transmitter includes a transmitting buffer (21) for temporarily storing the information received from a first bus (11) of N (N is a natural number) bits width and a transmitting input distributer (22) and a transmitting output distributer (23) respectively provided in the input side and output side of the transmitting system buffer (21). A receiver includes a receiving buffer (31) for temporarily storing the information received from the second bus (12) and for sending the information to the first bus (11) and a receiving input distributer (32) and a receiving distributer (33) respectively provided in the input side and output side of the receiving buffer. The transmitting buffer (21) has at least m (m is a natural number) buffers of N bits width. When the second bus (12) has N bits width, the transmitting input distributer (22) sequentially inputs the information sent from the first bus to m buffers and the transmitting output distributer (23) sequentially extracts the information input to the buffers to send to the second bus ( 12). When the second bus (12) has mN bits width, the transmitting input distributer (22) sequentially inputs the information sent from the first bus (11) to m buffers and the transmitting output distributer (23) simultaneously extracts the information into the m buffers to send to the second bus (12).
Inventors
- 👤 Makoto Okazaki
- 👤 Yuji Shibata
- 👤 Hisamitsu Tanihira
- 👤 Yoshiaki Wakimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:11
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
301 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer having at least m sub-buffers where m is a natural number, each of the m sub-buffers having N bits in width; first input distributing means, connected to the transmitting buffer, for receiving information including data and addresses from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer; second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus; the first input distributing means receiving the information from the first bus and inputting sequentially the information to the m sub-buffers; the first output distributing means, having at least first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus having mN bits in width; the first state comprising the second bus having mN bits in width, wherein m is equal to 1.0, and the first output distributing means sequentially extracting the information from the m transmitting buffers and sequentially transmitting the information to the second bus; and the second state comprising the second bus having mN bits in width, wherein m is not equal to 1.0, and the first output distributing means simultaneously extracting the information from the m sub-buffers and simultaneously transmitting the information to the second bus.
Claim 2
Dependent Claim
301 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer having at least m sub-buffers where m is a natural number, each of the m sub-buffers having N bits in width; first input distributing means, connected to the transmitting buffer, for receiving information including data and addresses from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer; second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus; the first input distributing means receiving the information from the first bus and inputting sequentially the information to the m sub-buffers; the first output distributing means, having at least first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus having mN bits in width; the first state comprising the second bus having mN bits in width, wherein m is equal to 1.0, and the first output distributing means sequentially extracting the information from the m transmitting buffers and sequentially transmitting the information to the second bus; and the second state comprising the second bus having mN bits in width, wherein m is not equal to 1.0, and the first output distributing means simultaneously extracting the information from the m sub-buffers and simultaneously transmitting the information to the second bus.
Claim 3
Dependent Claim
278 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer having an upper buffer and a lower buffer; first input distributing means, connected to the transmitting buffer, for receiving information from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer; second input distributing means, connected to the receiving buffer for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus; the first input distributing means receiving the information from the first bus and inputting alternately the information to the upper buffer and lower buffer; the first output distributing means, having first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus, having a bit width; the first state comprising the second bus having N bits in width and the first output distributing means alternately extracting the information from the upper buffer and the lower buffer and alternately transmitting the information to the second bus; and the second state comprising the second bus having 2N bits in width and the first output distributing means simultaneously extracting the information from the upper buffer and the lower buffer and simultaneously transmitting the information to the second bus.
Claim 4
Dependent Claim
278 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer having an upper buffer and a lower buffer; first input distributing means, connected to the transmitting buffer, for receiving information from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer; second input distributing means, connected to the receiving buffer for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus; the first input distributing means receiving the information from the first bus and inputting alternately the information to the upper buffer and lower buffer; the first output distributing means, having first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus, having a bit width; the first state comprising the second bus having N bits in width and the first output distributing means alternately extracting the information from the upper buffer and the lower buffer and alternately transmitting the information to the second bus; and the second state comprising the second bus having 2N bits in width and the first output distributing means simultaneously extracting the information from the upper buffer and the lower buffer and simultaneously transmitting the information to the second bus.
Claim 5
Dependent Claim
298 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer; first input distributing means, connected to the transmitting buffer, for receiving information including addresses and data from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer having m sub-buffers wherein m is a natural number, each of the m sub-buffers having N bits in width; second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus; the second input distributing means, having at least first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus having mN bits in width; the first state comprising the second bus having mN bits in width, wherein m is equal to 1.0, and the second input distributing means sequentially receiving the information from the second bus and sequentially transmitting the information to m sub-buffers; the second state comprising the second bus having mN bits in width, wherein m is not equal to 1.0, and the second input distributing means simultaneously receiving the information from the second bus and simultaneously transmitting the information to m sub-buffers; and the second output distributing means sequentially extracting the information from the m receiving buffers and sequentially transmitting the information to the first bus.
Claim 6
Dependent Claim
298 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer; first input distributing means, connected to the transmitting buffer, for receiving information including addresses and data from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer having m sub-buffers wherein m is a natural number, each of the m sub-buffers having N bits in width; second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus; the second input distributing means, having at least first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus having mN bits in width; the first state comprising the second bus having mN bits in width, wherein m is equal to 1.0, and the second input distributing means sequentially receiving the information from the second bus and sequentially transmitting the information to m sub-buffers; the second state comprising the second bus having mN bits in width, wherein m is not equal to 1.0, and the second input distributing means simultaneously receiving the information from the second bus and simultaneously transmitting the information to m sub-buffers; and the second output distributing means sequentially extracting the information from the m receiving buffers and sequentially transmitting the information to the first bus.
Claim 7
Dependent Claim
280 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer; first input distributing means, connected to the transmitting buffer, for receiving information from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer having an upper buffer and a lower buffer; second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer (31), for receiving the information from the receiving buffer and outputting the information to the first bus; the second input distributing means, having first and second states wherein each of the first and second states is selected by control signals indicative of the second bus, having a bit width; the first state comprising the second bus having N bits in width and the second input distributing means alternately receiving the information from the second bus and alternately transmitting the information to the upper buffer and the lower buffer; the second state comprising the second bus having 2N bits in width and the second input distributing means simultaneously inputting the information received from the second bus and simultaneously transmitting the information to the upper buffer and the lower buffer; and the second output distributing means alternately extracting the information from the upper buffer and lower buffer and transmitting the information to the first bus.
Claim 8
Dependent Claim
280 words
A bus interface circuit, comprising: a first bus having N bits in width, where N is a natural number; a second bus; transmitting means comprising: a transmitting buffer; first input distributing means, connected to the transmitting buffer, for receiving information from the first bus and inputting the information to the transmitting buffer, and first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus; receiving means comprising: a receiving buffer having an upper buffer and a lower buffer; second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and second output distributing means, connected to the receiving buffer (31), for receiving the information from the receiving buffer and outputting the information to the first bus; the second input distributing means, having first and second states wherein each of the first and second states is selected by control signals indicative of the second bus, having a bit width; the first state comprising the second bus having N bits in width and the second input distributing means alternately receiving the information from the second bus and alternately transmitting the information to the upper buffer and the lower buffer; the second state comprising the second bus having 2N bits in width and the second input distributing means simultaneously inputting the information received from the second bus and simultaneously transmitting the information to the upper buffer and the lower buffer; and the second output distributing means alternately extracting the information from the upper buffer and lower buffer and transmitting the information to the first bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-05 | 1998-03-07 | 1998-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-05 | 2002-03-07 | 2002-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-05 | 2006-03-07 | 2006-09-06 | $7700.00 | Window Closed / Lapsed |