Method of compressing and decompressing simulation data for generating a test program for testing a logic device

Claim 1

A method of reducing the simulation time and data storage requirements for a computer simulation of a logic device having a plurality of inputs and outputs, comprising the steps of: selecting an initial operating frequency for a logic device tester, said initial operating frequency having a corresponding period; selecting a sequence of input vectors to be applied to said plurality of inputs by said logic device tester for testing said logic device, wherein each input vector is to be applied for a finite duration equal to said period corresponding to said initial operating frequency, before a next input vector in said sequence is applied; associating a plurality of control bits with each of said sequence of input vectors; locating a series of redundant input vectors among said sequence of input vectors, wherein each input vector in said series is expected to generate an identical output vector on said plurality of outputs of said logic device; forming a subset to be provided to said computer simulation, of said sequence of input vectors by eliminating from said sequence of input vectors all but a first input vector of said located series of redundant input vectors; encoding a plurality of control bits associated with said first input vector of said located series; providing said computer simulation with said formed subset of input vectors along with the plurality of control bits associated with each input vector in said subset; causing said computer simulation to generate a set of simulated output vectors in response to said provided subset of input vectors; and forming a set of test vectors, wherein each test vector comprises an input vector from said formed subset of input vectors, a simulated output vector generated by said computer simulation in response to said input vector, and a plurality of control bits associated with said input vector.

Claim 2

A method of reducing the simulation time and data storage requirements for a computer simulation of a logic device having a plurality of inputs and outputs, comprising the steps of: selecting an initial operating frequency for a logic device tester, said initial operating frequency having a corresponding period; selecting a sequence of input vectors to be applied to said plurality of inputs by said logic device tester for testing said logic device, wherein each input vector is to be applied for a finite duration equal to said period corresponding to said initial operating frequency, before a next input vector in said sequence is applied; associating a plurality of control bits with each of said sequence of input vectors; locating a series of redundant input vectors among said sequence of input vectors, wherein each input vector in said series is expected to generate an identical output vector on said plurality of outputs of said logic device; forming a subset to be provided to said computer simulation, of said sequence of input vectors by eliminating from said sequence of input vectors all but a first input vector of said located series of redundant input vectors; encoding a plurality of control bits associated with said first input vector of said located series; providing said computer simulation with said formed subset of input vectors along with the plurality of control bits associated with each input vector in said subset; causing said computer simulation to generate a set of simulated output vectors in response to said provided subset of input vectors; and forming a set of test vectors, wherein each test vector comprises an input vector from said formed subset of input vectors, a simulated output vector generated by said computer simulation in response to said input vector, and a plurality of control bits associated with said input vector.