Leading one anticipator and floating point addition/subtraction apparatus

Claim 2

A leading one anticipator, comprising: first means for generating an anticipated bit-discard amount within a 1-bit error; second means for generating information on borrow propagation from a lower bit side; third means for handling the anticipated bit-discard amount, using the borrow propagation information, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of the borrow.

Claim 3

A leading one anticipator, comprising: first means for generating an anticipated bit-discard within a 1-bit error and outputting whether a result of addition/subtraction instruction is positive or negative; second means for generating information on borrow propagation from a lower bit side, distinguishing into two kinds of a borrow resulting from a subtraction (a minuend-a subtrahend) and a borrow resulting from a subtraction (a subtrahend-a minuend); and third means for handling the anticipated bit-discard amount, using the information on borrow propagation, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of borrow resulting from the subtraction that the minuend-the subtrahend when a result of subtraction is positive and according to the presence of borrow resulting from the subtraction that the subtrahend-the minuend when a result of subtraction is negative.

Claim 4

A leading one anticipator, comprising: first means for generating an anticipated bit-discard within a 1-bit error and outputting whether a result of addition/subtraction instruction is positive or negative; second means for generating information on borrow propagation from a lower bit side, distinguishing into two kinds of a borrow resulting from a subtraction (a minuend-a subtrahend) and a borrow resulting from a subtraction (a subtrahend-a minuend); and third means for handling the anticipated bit-discard amount, using the information on borrow propagation, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of borrow resulting from the subtraction that the minuend-the subtrahend when a result of subtraction is positive and according to the presence of borrow resulting from the subtraction that the subtrahend-the minuend when a result of subtraction is negative.

Claim 5

The leading one anticipator as claimed in claim 2, wherein: said first means subtracts per a digit a minuend X of i-digit binary numeral and a subtrahend Y of j-digit binary numeral (i and j are natural numerals) and generates a redundant binary numeral Zsd each digit of which is composed of (-1, 0, 1) as a result of subtraction; said second means generates an intermediate carry Ck and an intermediate sum Sk according a formula Zsdk=2Ck+Sk so that Ck=Zsdk when Zsdk+1="1" or "-1" and Ck=0 when Zsdk+1="0", using a redundant binary numeral Zsdk at a k-bit lower bit than the redundant binary numeral Zsd and a redundant binary numeral Zsdk+1 at a (k+1)-bit lower bit than the redundant binary numeral Zsd (k is an integer wherein a least significant bit is expressed as k=0); and said third means generates a redundant binary numeral ZZk which is "0" when a result of addition per a digit of an intermediate carry Ck-1 from a lower digit and an intermediate sum Sk is 0, "1" when the result of addition is 1 and "-1" when the result of addition is -1.

Claim 6

A floating point addition/subtraction apparatus for performing an addition or a subtraction of two operands of the floating point type each having a mantissa part, an exponent part and a sign part, comprising: an addition/subtraction circuit and a leading one anticipator into which two operands of mantissa values after digit alignment are input, respectively; a barrel shifter into which an output of said addition/subtraction circuit is input; and a priority encoder, into which a numeral value output from said leading one anticipator is input, for obtaining a number of successive zeros from a most significant bit thereof, wherein an output of said addition/subtraction circuit input into said barrel shifter is shifted and outputted using an output of said priority encoder; said leading one anticipator comprising: first means for generating an anticipated bit-discard amount within a 1-bit error; second means for generating information on borrow propagation from a lower bit side; and third means for handling the anticipated bit-discard amount, using the borrow propagation information, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of the borrow.

Claim 7

A floating point addition/subtraction apparatus for performing an addition or a subtraction of two operands of the floating point type each having a mantissa part, an exponent part and a sign part, comprising: an addition/subtraction circuit and a leading one anticipator into which two operands of mantissa values after digit alignment are input, respectively; a barrel shifter into which an output of said addition/subtraction circuit is input; and a priority encoder, into which a numeral value output from said leading one anticipator is input, for obtaining a number of successive zeros from a most significant bit thereof, wherein an output of said addition/subtraction circuit input into said barrel shifter is shifted and outputted using an output of said priority encoder; said leading one anticipator comprising: first means for generating an anticipated bit-discard amount within a 1-bit error; second means for generating information on borrow propagation from a lower bit side; and third means for handling the anticipated bit-discard amount, using the borrow propagation information, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of the borrow.

Claim 8

A floating point addition/subtraction apparatus for performing an addition or subtraction of two operands of the floating point type each having a mantissa part, an exponent part and a sign part, comprising: an addition/subtraction circuit and a leading one anticipator into which two operands of mantissa values after digit alignment are input, respectively; a barrel shifter into which an output of said addition/subtraction circuit is input; and a priority encoder, into which a numeral value output from said leading one anticipator is input, for obtaining a number of successive zeros from a most significant bit thereof, wherein an output of said addition/subtraction circuit input into said barrel shifter is shifted and outputted using an output of said priority encoder; said leading one anticipator comprising: first means for generating an anticipated bit-discard within a 1-bit error and outputting whether a result of an addition/subtraction instruction is positive or negative; second means for generating information on borrow propagation from a lower bit side, distinguishing into two kinds of a borrow resulting from a subtraction (a minuend-a subtrahend) and a borrow resulting from a subtraction (a subtrahend-a minuend); and third means for handling the anticipated bit-discard amount, using the information on borrow propagation, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of borrow resulting from the subtraction of the minuend minus the subtrahend when the result of the subtraction is positive and according to the presence of borrow resulting from the subtraction of the subtrahend minus the minuend when the result of the subtraction is negative.

Claim 9

A floating point addition/subtraction apparatus for performing an addition or subtraction of two operands of the floating point type each having a mantissa part, an exponent part and a sign part, comprising: an addition/subtraction circuit and a leading one anticipator into which two operands of mantissa values after digit alignment are input, respectively; a barrel shifter into which an output of said addition/subtraction circuit is input; and a priority encoder, into which a numeral value output from said leading one anticipator is input, for obtaining a number of successive zeros from a most significant bit thereof, wherein an output of said addition/subtraction circuit input into said barrel shifter is shifted and outputted using an output of said priority encoder; said leading one anticipator comprising: first means for generating an anticipated bit-discard within a 1-bit error and outputting whether a result of an addition/subtraction instruction is positive or negative; second means for generating information on borrow propagation from a lower bit side, distinguishing into two kinds of a borrow resulting from a subtraction (a minuend-a subtrahend) and a borrow resulting from a subtraction (a subtrahend-a minuend); and third means for handling the anticipated bit-discard amount, using the information on borrow propagation, wherein said third means outputs a bit shift amount for normalizing a mantissa value in which the bit-discard occurs based on an anticipated bit-discard amount obtained by said first means according to the presence of borrow resulting from the subtraction of the minuend minus the subtrahend when the result of the subtraction is positive and according to the presence of borrow resulting from the subtraction of the subtrahend minus the minuend when the result of the subtraction is negative.